參數(shù)資料
型號: LXP730LE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 44/70頁
文件大?。?/td> 1007K
代理商: LXP730LE
LXP730
Multi-Rate DSL Framer
44
Datasheet
Figure 23. Microprocessor Write Cycle - Intel Mode
Table 21.
Microprocessor Write Cycle Specifications
Intel Mode (See Figure 23)
Parameter
Sym
t
ASU
Min
Typ
1
Max
Unit
Test Conditions
Address setup time
30
ns
Referenced from falling edge of ALE
Address latch enable pulse
width
t
APW
30
ns
D<0:7> setup time
t
W
SU
30
ns
Referenced from rising edge of CS or
WR
D<0:7> hold time
t
DHT
10
ns
Referenced from rising edge of CS or
WR
CS width
t
CPW
t
WPW
4/MCLK
s
WR width
4/MCLK
s
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
t
WPW
AD<0:7>
CS
t
CPW
t
DHT
t
WSU
WR
t
ASU
t
APW
ALE
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