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參數(shù)資料
| 型號： | LXP730LE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 14/70頁 |
| 文件大小： | 1007K |
| 代理商： | LXP730LE |
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LXP730
—
Multi-Rate DSL Framer
14
Datasheet
2.0
Functional Description
2.1
LXP730 Nx64 Framer
The LXP730 is designed to multiplex/demultiplex two payload sources to/from a DSL stream, and
add/recover overhead data for link control. Several popular interfaces are provided to support a
variety of applications.
The two major categories of payload supported are synchronous (i.e. voice-frequency data - PCM)
and asynchronous (i.e. digital data - Packet/Cell). The LXP730 supports
N
x64 kbps channels in the
DSL with
N
= 4 to 18. The LXP730 consists of the following functional blocks as shown on page
1:
Time Slot Interchange (TSI)
PCM-Bus Interface
Codec Interface
T1/E1 Interface
Asynchronous Data Port Interface (ADPI)
Microprocessor Interface
Overhead Serial I/O (OSIO) Interface
SK70725/SK70721 (MDSL) Interface
All Digital PLL (ADPLL)
Clock Generation and Distribution
The terms Local and Remote are used in this document to designate the two ends of a DSL link.
The Local is usually the master in that it initiates the link startup and can control the actions and
configuration of the Remote. There are several equivalent nomenclatures in the Telecom industry.
Some of these are, respectively: CO and CPE, or HTU-C and HTU-R, or LTU and NTU.
The following is a description of the LXP730 functional blocks.
2.2
Time Slot Interchange (TSI)
The Time Slot Interchange (TSI) is the central module of the LXP730 Nx64 framer. The TSI maps
payload to the available DSL N-channels for transport across the loop.
The TSI uses register settings to select time slots to map into the N MDSL channels. The total
number of available payload channels is
N
and is set by the N_MDSL register (00h), with selected
valid values from 4 to 18. Each of the 18 Nx registers (01h -012h) is used to select the payload
source, and if applicable, the PCM time slot assigned to the register
’
s corresponding MDSL
channel.
In the MX direction (from the TSI to the MDSL Interface), the TSI multiplexes the payload sources
into the MX elastic store (MX ES). The payload and overhead are multiplexed into the DSL stream
for loop transport.
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