參數(shù)資料
型號： LXP730LE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 4/70頁
文件大小： 1007K
代理商： LXP730LE
LXP730 —
Multi-Rate DSL Framer
4
Datasheet
5.2.9
5.2.10 Channel 10.............................................................................................52
5.2.11 Channel 11.............................................................................................52
5.2.12 Channel 12.............................................................................................52
5.2.13 Channel 13.............................................................................................53
5.2.14 Channel 14.............................................................................................53
5.2.15 Channel 15.............................................................................................53
5.2.16 Channel 16.............................................................................................54
5.2.17 Channel 17.............................................................................................54
5.2.18 Channel 18.............................................................................................54
Reserved Registers (3 bytes)..............................................................................55
Wander Reduction Register................................................................................55
FIFO/Miscellaneous Control Register .................................................................55
Slip Buffer Lower Threshold Register .................................................................56
Slip Buffer Upper Threshold Register .................................................................57
Version Register..................................................................................................57
Internal Clock Control Registers (4 bytes) ..........................................................57
5.9.1
ADPLL Control 1 ....................................................................................57
5.9.2
ADPLL Control 2 ....................................................................................58
5.9.3
ADPLL Control 3 ....................................................................................58
5.9.4
MCLK Divide ..........................................................................................58
Programmable Idle Code Byte............................................................................58
PCM Configuration Registers..............................................................................59
5.11.1 PCM1 Configuration...............................................................................59
5.11.2 PCM2 Configuration...............................................................................59
Codec Configuration Register.............................................................................60
Overhead Registers (25 bytes)...........................................................................60
5.13.1 Miscellaneous Control............................................................................60
5.13.2 Overhead Configuration.........................................................................61
5.13.3 CRC Error Counter.................................................................................61
5.13.4 FEBE Error Counter...............................................................................62
5.13.5 CRC - FEBE - LOS Status .....................................................................62
5.13.6 MX Overhead Bits 1 - 8..........................................................................62
5.13.7 MX Overhead Bits 9 - 16........................................................................63
5.13.8 MX Overhead Bits 17 - 24......................................................................63
5.13.9 MX Overhead Bits 25 - 32......................................................................63
5.13.10 MX Z Bits 1 - 8 .......................................................................................64
5.13.11 MX Z Bits 9 - 16 .....................................................................................64
5.13.12 MX Z Bits 17 - 24 ...................................................................................64
5.13.13 MX Z Bits 25 - 32 ...................................................................................65
5.13.14 MX Z Bits 33 - 40 ...................................................................................65
5.13.15 MX Z Bits 41 - 48 ...................................................................................65
5.13.16 DX Overhead Bits 1 - 8 ..........................................................................65
5.13.17 DX Overhead Bits 9 - 16 ........................................................................66
5.13.18 DX Overhead Bits 17 - 24 ......................................................................66
5.13.19 DX Overhead Bits 25 - 32 ......................................................................66
5.13.20 DX Z Bits 1 - 8........................................................................................67
5.13.21 DX Z Bits 9 - 16......................................................................................67
5.13.22 DX Z Bits 17 - 24....................................................................................67
5.13.23 DX Z Bits 25 - 32....................................................................................68
Channel 9...............................................................................................51
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
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