參數(shù)資料
型號: LXP730LE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 45/70頁
文件大?。?/td> 1007K
代理商: LXP730LE
Multi-Rate DSL Framer
LXP730
Datasheet
45
Figure 24. Microprocessor Read Cycle - Intel Mode
Table 22. Microprocessor Read Cycle Specifications
Intel Mode (See Figure 24)
Parameter
Sym
t
ASU
t
APW
Min
Typ
1
Max
Unit
Test Conditions
Address setup time
30
ns
Referenced from falling edge of ALE
Address latch enable pulse
width
30
ns
D<0:7> valid after CS, RD
assertion
t
D
O
60
ns
Referenced from the falling edge of RD
and CS
D<0:7> keep valid after CS,
RD negation
t
D
HT
10
20
ns
Referenced from rising edge of CS or
RD
Allowed width of CS
t
CPW
t
RPW
4/MCLK
s
Allowed width of RD
4/MCLK
s
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Table 23. MCLK Frequency and Tolerance Specification
Parameter
Sym
F
mclk
Min
Typ
1
Max
Unit
Test Conditions
MCLK frequency
24.832
MHz
MCLK duty cycle
M
DC
40
60
%
1. Typical values are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Figure 25. Reset Timing
AD<0:7>
CS
RD
t
CPW
t
RPW
ALE
t
DO
t
DHT
t
ASU
t
APW
t
RESET
RESET
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