參數(shù)資料
型號(hào): LXP730LE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 29/70頁(yè)
文件大?。?/td> 1007K
代理商: LXP730LE
Multi-Rate DSL Framer
LXP730
Datasheet
29
Figure 8
shows a more traditional DSL application to carry phone traffic over a longer distance on
a single copper pair. The LXP730 supports the pleisiochronous nature of T1/E1 traffic.
3.1.1
IOM Interface Circuitry
The LXP730 uses a frame pulse in the second cycle of the two clocks per data bit timing. This is
directly compatible with the ST electrical interface. The IOM interfaces use the first clock cycle for
the frame pulse. The circuit in
Figure 9
shows how to adapt the LXP730 to the IOM bus. Note that
even though the circuit is the same for the PCM master or slave modes, there is a difference in the
connections to the LXP730 and the IOM device.
Figure 7. Pair Gain Transport
LXP730
Framer
CDATI
CDATO
CCLK
2.048 Mbps
PCM Highway
FRM1
FRMn
Signalling Control
SIO
Indicators
64 kbps Voiceband
Channels
QUATCLK
BITCLK
TDATA
RDATA
ACTIVE
SK70725/21
Data Pump
Combo
Codec
Combo
Codec
Figure 8. T1/E1 Fractional Transport
LXP730
Framer
PDATI
PCLK
PDO
CCLK
T1/E1 Framer
FRM1
PFRM
Microprocessor
TDATA
RDATA
BITCLK
QUATCLK
SK70725/21
Data Pump
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