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參數(shù)資料
| 型號(hào)： | LXP730LE |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 30/70頁(yè) |
| 文件大?。?/td> | 1007K |
| 代理商： | LXP730LE |
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LXP730
—
Multi-Rate DSL Framer
30
Datasheet
3.1.2
Handling TIP/RING Reversal in Early Version of SK70725
The early version of the SK70725 data pump device has an error in the Master (CO) mode. The
QUAT_CLK is not aligned correctly with the RDATA for the sign and magnitude bits. When there
is no TIP/RING reversal, the LXP730 is able to correctly parse the data bits. However, when TIP/
RING reversal has occurred the LXP730 detects that the sign bit is inverted by detecting the
inverted Frame Sync Word (FSW) pattern. The LXP730 then uses the QUAT_CLK to determine
which bit to invert. The sign bit is already inverted and the LXP730 inverts the magnitude bit.
This problem does not occur in the Slave (CPE) mode of the SK70725. The SK70725 has the
ability to invert the received data pulses inside itself. This is done by setting bit 7 of the register
WR2. The following procedure takes advantage of how the LXP730 reacts during the error
condition and the ability to invert the data stream from the SK70725. The procedure uses one of
the Z-bit bytes after frame sync has been achieved to determine if there is a tip-ring reversal at the
LTU. DXZ2 and MXZ2 are good choices and are used only at the start up time. The TIP/RING
reversal indicator in the SK70725 does not have any meaning in mode 0, as the transparent mode
needed to work with LXP730. This procedure can be left in the code for the future SK70725
revision. The procedure also shows how to handle BELB from the CPE end.
TIP/RING Reversal Procedure:
1. Start.
2. Initialize the LXP730s for required configuration.
3. Activate the SK70725s.
4. Send the test pattern MXZ2 from the NTU side. MXZ2 = AAh.
5. If DXZ2 = AAh is received on LTU TIP/RING lines are straight and system is ready for
transmission. Go to step 7.
Figure 9. IOM Adaption Circuitry
D
Q
1/2
74HC74
D
Q
1/2
74HC74
D
Q
1/2
74HC74
D
Q
1/2
74HC74
PFRM
PFRM Delayed
PFRM
Master PCM
FRAME
PCLK
PCLK
LXP730 PCM Master
PCM_FS_POS = 1
LXP730 PCM Slave
PCM_FS_POS = 0
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