參數(shù)資料
型號(hào)： LXP730LE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 13/70頁
文件大小： 1007K
代理商： LXP730LE
Multi-Rate DSL Framer
—
LXP730
Datasheet
13
44
OSOF
DO
OSOF.
Overhead Serial Output Flag, output. Indicates the first bit of OSIO output
frame.
50
OSIF
DO
OSIF.
Overhead Serial Input Flag, output. Indicates the first bit of OSIO input frame.
45
TDATA
DO
TDATA.
Transmit Data, output. Connect to SK70725.
47
RDATA
DI
RDATA.
Receive Data, input. Connect to SK70725.
46
QUATCLK
DI
QUATCLK.
Quaternary alignment Clock, input. Connect to SK70725.
43
BITCLK
DI
BITCLK.
Bit Clock, input. Connect to SK70725.
13
PFRM / FRMIN /
Z
0
DI,DO,DI
PFRM.
PCM frame pulse: input for PCM slave, output for PCM master. Alignment
signal for the first time slot for both PDI and PDO. /FRMIN. Frame In, for T1/E1
application, input. /Z
o
. Bit zero of the 3-bit word used to specify the number of Z bits
in the Hardware mode, input.
12
PDI / T1E1I / Z
1
PU,DI,
DI
PDI.
PCM Data In, input.
/T1E1I.
T1 or E1 Input data, input. /
Z
1
.
Bit one of the 3-bit
word used to specify the number of Z bits in the Hardware mode, input.
15
PDO / T1E1O / Z
2
TO,TO,DI
PDO.
PCM Data Out, tri-stateable output.
/T1E1O.
T1 or E1 Output data, tri-
stateable output. /
Z
.
Bit two of the 3-bit word used to specify the number of Z bits in
the Hardware mode, input.
14
PCLK/TCLKI
DI/O
PCLK.
PCM clock: input for PCM slave, output for PCM master.
/TCLKI.
Transport
Clock In, for T1/E1 application, 1.544MHZ - T1, 2.048MHz - E1, input.
Table 1. LXP730 Pin Descriptions (Continued)
Pin
Symbol
Type
1
Description
1. AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; NC = No Clamp. Pad will not clamp input in
the absence of power; PU = Input contains pull-up; PD = Input contains pull-down; I/O = Input/Output; OD = Open Drain
Output;
TO = Tri-State Output.
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