參數(shù)資料
型號： LXP730LE
元件分類： 通信及網(wǎng)絡
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 18/70頁
文件大小： 1007K
代理商： LXP730LE
LXP730
—
Multi-Rate DSL Framer
18
Datasheet
2.7
Overhead Interface
The LXP730 provides two options for the interface to insert and receive overhead data for the link:
via an external serial interface or through the microprocessor register interface. The data can either
be user defined or partially predefined as described in
“
MDSL Overhead Definition
”
on page 23
.
The overhead channel is used for signalling, status flags, loopback control, and diagnostic
messaging between the Local and Remote ends of a MDSL link. The LXP730 provides the
transparent channel for the overhead data and does not interpret the protocol operation.
The F-bits in the fractional T1 mode are not part of the overhead.
2.7.1
Overhead Serial I/O (OSIO)
The OSIO interface is the default overhead access for both the MPC and HWC operational modes.
The serial interface provides six separate pins for data in (OSDI), data out (OSDO), clock-in
(OSDICK) clock-out (OSDOCK), start flag in (OSIF), and start flag out (OSOF). The use of the
first four pins is compatible with the bit operation protocol (BOP) for HDLC devices. The two flag
pins (OSIF and OSOF) provide indications of the start of a MDSL frame and may used with
custom overhead handling devices. The flag signals are coincident with the first overhead bit in the
MDSL frame.
The LXP730 controls both of the clocks, and thus, the data flow. The clocks will be gapped due to
the availability of bit positions in the DSL data stream. The OSIO may be disabled in the MPC
mode by setting the Par/Ser bit in the OVRHD_SEL register (24h). OSIF and OSOF will continue
to operate.
The defined bits (except the indc_r bit) go to the microprocessor interface registers. The undefined
bits (plus the indc_r bit) go to the OSIO interface. This allows a separate transport for HDLC
devices while maintaining DSL performance monitoring.
2.7.2
MDSL Overhead Microprocessor Interface
The MDSL overhead microprocessor interface mode uses internal registers to provide the access to
insert and receive overhead data for the link. The Par/Ser bit must be set to access the contents of
the overhead and Z bit registers. Interrupts may be used to synchronize the contents with the
MDSL link. The data can either be user defined or partially predefined as described in
“
MDSL
Overhead Definition
”
on page 23
. Microprocessor writes to defined bits have no effect, with the
exception of the indc_r bit.
The registers for the OH and Z bits are double buffered for both the MX and DX sections. When
the OHMX bit is set in the INT_STAT, 3Fh, register, the values in the user assessable MX registers
are latched into an internal set of registers, and then serially shift throughout the frame. The user
has a nominal 6 ms to update the MX registers before they are latched again for transport.
Likewise, the DX registers hold their values until the OHDX bit is set, then the overhead data from
the latest frame is available. The user again has a nominal 6 ms to read the DX data before it is over
written.
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