參數(shù)資料
型號(hào)： LXP730LE
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 17/70頁(yè)
文件大小： 1007K
代理商： LXP730LE
Multi-Rate DSL Framer
—
LXP730
Datasheet
17
The LXP730 generates the codec clock and the framing pulses for eighteen (18) codecs from the
selected reference. Selecting codec timeslot 0 in an Nx register corresponds to FRMSYNC1, 1 to
FRMSYNC2, etc. In HWC mode, the FRMSYNC pins are automatically assigned with the
programming of the Nx pins. The number of codec time slots per frame is variable from 4 to 64.
This is programmed by setting the six MAXCCHN bits in the COD_CFG register (22h) with the
value n-1 number time slots.
Codec selection for a MDSL channel is accomplished by setting the CH_CFG bits in the Nx
register to
‘
00
’
(binary).
2.5
T1/E1 Interface
The LXP730 supports T1/E1 framer interfaces by using a hybrid of the PCM and codec interfaces
to transport pleisiochronous data.
The PCM interface is used in its slave mode to connect a T1/E1 framer and its TxData (T1E1O),
RxData (T1E1I), RxCLK (TCLKI) and FramePulseOut (FRMIN). The slip buffer must be in the
bypass mode.
The codec interface is used in its slave mode to derive the FramePulseIn (FRMOUT) and TxCLK
(TCLKO) to the T1/E1 framer. The derived T1/E1 FRMOUT tracks the MDSL frame rate from the
DSL, and in cases where framing is lost, the DX tracking circuits slowly reacquire to prevent a
drastic change in the output frame frequency.
The PCM and codec sections must each be configured through registers to handle the T1/E1
pleisiochronous data.
For T1, only
N
=12 or fractional T1 is supported. In T1, the only workable value for the
PCM_CFG2 register is 98h. The MX T1 F-bits must be part of the data stream coming from the
external T1 framer. The 12 unused DX T1 time slots are filled with the value programmed in the
IDLE register if the TFI bit (bit 0) is set to 0.
Key features of the T1E1 interface are:
Framer interfaces: DS2141and DS2143
Data rates: 1544 and 2048 kbps
Clock rates: 1544 and 2048 kHz
2.6
Asynchronous Data Port Interface (ADPI)
The LXP730 supports a serial method for the Asynchronous Data Port Interface (ADPI). The ADPI
is available only in the MPC operating mode. MDSL channels are programmed for ADPI by
setting the CH_CFG bits to
‘
11
’
(binary) in the desired Nx register. The operation of the ADPI is
mutually exclusive with the LXP730 codec frame sync pins (FRMSYNC7-10).
The serial ADPI mode provides separate pins for data in, data out, clock-in and clock-out. This is
compatible with the bit operation protocol (BOP) for HDLC devices. The LXP730 controls both of
the clocks, and therefore, the data flow. The LXP730 moves the bits in and out in 8-bit groups. The
maximum clock rate for the bit-to-bit transfer is set by the SAPCLKDIV bits in the FIFO_MISC
register. This allows the clocks to run at MCLK
÷
2 or slower. The groups of clock pulses will be
gapped due to the availability of bit positions in the DSL data stream.
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