參數(shù)資料
型號: LXP730LE
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 59/70頁
文件大?。?/td> 1007K
代理商: LXP730LE
Multi-Rate DSL Framer
LXP730
Datasheet
59
5.11
PCM Configuration Registers
5.11.1
PCM1 Configuration
Address: 20
Abbreviation: PCM_CFG1
Read/Write
5.11.2
PCM2 Configuration
Address: 21
Abbreviation: PCM_CFG2
Read/Write
Table 54. Programmable Idle Code Byte
Bit
Name
Default
Description
<7:0>
IDLE <7:0>
FFh
Programmable idle code. This 8 bit code contains the bit used for
channel blocking.
Table 55. PCM 1 Configuration Bits
Bit
Name
Default
Description
7
PCLKMODE
0
Set to
0
for 1x clock, set to
1
for 2x clock.
<6:5>
PCLKMUX
10b
PCM Clock Mux
00 External Pin, PCLK pin-14 (PCM Slave)
01 Internal ADPLL (PCM Master)
10 MCLK divided by PROG_DIV register
11 ADPLL output divided by PROG_DIV register
4
DCE
0
Data clock edge, 0 = sample input data on falling edge - output data
on rising edge, 1 = sample input on rising edge - output data on
falling edge.
3
FINV
0
Frame Sync Pulse polarity, 0 = Active low, 1 = Active high.
2
FE
0
Frame Clock Edge, 0 = sample frame sync on falling edge - output
on rising edge, 1 = sample frame sync on rising edge - output on
falling edge.
1
SBBP
1
Slip buffer ByPass, 0 = Slip buffer active, 1 = Slip buffer bypassed.
0
TFI
0
Tri-state for IDLE code, 0 = pass IDLE to PCM, 1 = Tri-state PCM for
IDLE.
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