Multi-Rate DSL Framer
—
LXP730
Datasheet
15
In the DX direction (from the MSDL Interface to the TSI), the TSI reads from the DX elastic store
(DX ES) and demultiplexes the loop data into its payload data sources.
Synchronous payload sources are typically 8-bit serial time slots, cascaded together with each
source repeating every 125 μsec (i.e. 8 kHz). A framing pulse, separate from the data signal,
signifies the start of a frame. A 2.048 Mbps data stream has 32 time slot sources, while a 1.544
Mbps data stream has 24 time slot sources plus one extra bit for framing.
When the PCM or codec interfaces are running, the framing pulses are used by the TSI to initialize
operation to the MX ES. The MX ES and DX ES have triple buffering schemes that prevent the
loss of data. The PCM/codec interfaces typically produce high speed data bursts while the MDSL
interface runs at a slower though irregular rate.
Asynchronous data is typically a sequence of bytes which have no explicit timing relationship
between them. Asynchronous Data Port Interface (ADPI) bytes may be inserted into payload slots
that are not carrying PCM data. ADPI bytes are inserted into the DSL stream in the order they are
received from the interface.
Channel blocking on a MDSL channel is achieved by setting the CH_CFG bits in the Nx register to
01. The transported value for that MDSL channel will be the one stored in the IDLE register.
The TSI uses the MCLK clock to synchronize to the various interfaces. The MCLK frequency must
be at least three times the highest interface clock frequency for the TSI to function properly. There
are other considerations to select the operating frequency of MCLK when using the internal
ADPLL.
2.3
PCM-Bus Interface
The LXP730 provides a generic interface for common PCM-bus configurations and can either be
master or slave to these PCM busses. Some of the key features that allow flexibility are:
Clock at 1x or 2x the data rate
Programmable number of bytes per frame; 8, 16, 32, 64
Programmable clock and frame pulse polarities
These features allow interfacing to standard PCM styles such as: ST, IOM, IOM2 (see
Figure 9
for
circuit) and CHI. The data rates can range from 256 kbps to 4096 kbps. The clock rates can range
from 256 kHz to 8196 kHz.
The range of permissible PCM time slots are 0 to 31 for a 2.048 Mbps backplane and 0 to 63 for a
4.096 Mbps backplane for a total number of time slots up to the maximum number N. PCM time
slots must be assigned in ascending order to MDSL channels. The value set in the TS-bits in the Nx
registers select the PCM timeslot to go into the xth MDSL channel.
There is a limitation of the disparity allowed between the PCM clock and the BIT_CLK. For N = 4,
the PCM bit rate cannot exceed 2 Mbps. To use a 4 Mbps PCM interface the NMDSL setting must
be at least 6 channels.
On these busses, the input and output data streams are synchronized to the same clock. A slip
buffer is present on the receive side to accommodate the differences in the PCM clock frequencies
of the two ends of the MDSL line.