參數(shù)資料
型號(hào)： LXP730LE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 3/70頁
文件大?。?/td> 1007K
代理商： LXP730LE
Datasheet
3
Multi-Rate DSL Framer — LXP730
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
...........................................................................................14
2.1
LXP730 Nx64 Framer..........................................................................................14
2.2
Time Slot Interchange (TSI)................................................................................14
2.3
PCM-Bus Interface..............................................................................................15
2.4
Codec Interface...................................................................................................16
2.5
T1/E1 Interface....................................................................................................17
2.6
Asynchronous Data Port Interface (ADPI)...........................................................17
2.7
Overhead Interface..............................................................................................18
2.7.1
Overhead Serial I/O (OSIO) ...................................................................18
2.7.2
MDSL Overhead
Μιχροπροχεσσορ
Interface.........................................18
2.8
MDSL Interface ...................................................................................................19
2.9
All Digital PLL (ADPLL).......................................................................................20
2.9.1
ADPLL Performance: The Selection of Kloop ........................................20
2.9.2
ADPLL Center Frequency: The computation of CFREQ........................21
2.10
Clock Generation and Distribution.......................................................................21
2.11
Modes of Operation.............................................................................................22
2.11.1 Microprocessor Control (MPC) Mode.....................................................22
2.11.2 Hardware Control (HWC) Mode .............................................................23
2.12
MDSL Overhead Definition..................................................................................23
2.12.1 Predefined Overhead.............................................................................24
2.12.2 Z bits.......................................................................................................24
2.13
MDSL Frame Format...........................................................................................25
2.14
Startup Operation................................................................................................26
2.15
Activation State Machine.....................................................................................27
Application Information
.........................................................................................28
3.1
Typical Applications.............................................................................................28
3.1.1
IOM Interface Circuitry ...........................................................................29
3.1.2
Handling TIP/RING Reversal in Early Version of SK70725 ...................30
3.1.3
DSL System Loopbacks.........................................................................31
3.1.4
Using Multiple Devices on an Interrupt Line...........................................32
Test Specifications
..................................................................................................33
Register Definitions
.................................................................................................47
5.1
Number MDSL Channels Register......................................................................48
5.2
MDSL Channel Configuration Registers (18 bytes) ............................................49
5.2.1
Channel 1...............................................................................................49
5.2.2
Channel 2...............................................................................................49
5.2.3
Channel 3...............................................................................................49
5.2.4
Channel 4...............................................................................................50
5.2.5
Channel 5...............................................................................................50
5.2.6
Channel 6...............................................................................................50
5.2.7
Channel 7...............................................................................................51
5.2.8
Channel 8...............................................................................................51
3.0
4.0
5.0
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