參數(shù)資料
型號(hào)： LXP730LE
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 23/70頁(yè)
文件大?。?/td> 1007K
代理商： LXP730LE
Multi-Rate DSL Framer
—
LXP730
Datasheet
23
address is presented to the AD pins and internally latched with ALE, then the data is either read
from or written to the device. ALE may be held high for non-multiplexed address and data
operation in the Intel mode for use of the WR and RD signals.
One interrupt pin is provided. Registers are provided for enabling/disabling the interrupts and
monitoring the status of the interrupt signals.
In the MPC mode, both the PCM and Codec/Data Port interfaces may be used simultaneously. The
assignment of the 64 kbps timeslots from the interfaces to the DSL is controlled by the TSI (Time
Slot Interchange) block. This feature allows data from two different sources to be transported over
the DSL.
2.11.2
Hardware Control (HWC) Mode
This mode provides an operational method to run only the codec and OSIO interface without a
microprocessor. Pins are provided to select the number (N) of 64 kbps channels to be transported.
The following Error/Status flags output pins are provided: LINK_ACTIVE, CRC_ERR and FEBE.
RESET, HTUC/HUTR and RUN-STOP control signals (input pins) are provided.
These pins are shared with the microprocessor mode pins. The HWC mode is selected by pulling
the WR, RD, CS and ALE pins Low and the MOTEL pin High.
Only the codec and OSIO interfaces are accessible in the HWC mode. The first
N
codec frame sync
pins are active in sequence from 1 to N. As shown in
Table 5
, pins N1 through N4 are used to select
the quantity of codecs supported and to select the proper MDSL frame format. The N0 pin is not
used since
N
is always an even number in the HWC mode. The codec interface runs only at the
2.048 MHz 1x clock in the HWC mode.
2.12
MDSL Overhead Definition
The MDSL overhead bits do not carry any payload values but are used for exchanging messaging
and signalling information between the two ends of the DSL link. The overhead bits are divided
into two categories; OH and Z bits.
The OH bits are defined in both the ETSI ERT/ETS-152 and ANSI T1E1.4/94-006 standards.
These usually have specific definitions. In the LXP730, the OH bits may be partially defined,
according to the standards, or totally user definable which is referred to as transparent mode.
The LXP730 supports DSL OH bits in four modes:
Table 5. Pin settings for HWC DSL Line Rates
Number of
MDSL Channels
Pin
N4
N3
N2
N1
4
0
0
0
1
6
0
0
1
0
8
0
0
1
1
10
0
1
0
0
12
0
1
0
1
18
1
0
0
0
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