參數(shù)資料
型號： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁數(shù)： 46/59頁
文件大小： 660K
代理商： HMS77C2001
HMS77C2000/2001
Nov. 2002 Ver 1.1
43
device from the malfunction due to Power Noise.
The bit0(PFDEN) of OSCCAL register activates the PFD
Circuit, and bit1(PFDF) indicates ‘power fail detection sit-
uation”. The normal detection level is typically 2.7V. Fig-
ure 12-14 shows a “power fail detection situations”.
Note:
The PFD circuit is not implemented on the in circuit
emulator, user can not experiment with it. There
fore, after final development user program, this
function may be experimented on OTP.
12.13 IN-CIRCUIT SERIAL PROGRAMMING
The HMS77C2000 and HMS77C2001 microcontrollers
with EPROM program memory can be serially pro-
grammed while in the end application circuit. This is sim-
ply done with two lines for clock and data, and three other
lines for power, ground, and the programming voltage.
This allows customers to manufacture boards with unpro-
grammed devices, and then program the microcontroller
just before shipping the product. This also allows the most
FIGURE 12-13 OSCCAL REGISTER
CAL4
R/W
CAL3
R/W
CAL2
R/W
CAL1
R/W
CAL0
R/W
-
R/W
PFDF
R/W
PFDEN
R/W
bit7
6
bit0
5
4
3
2
1
CAL4~CAL0
: Calibration Bits
11111 = High frequency
10000 = Middle frequency
00000 = Low frequency
PFDF
: Power-fail detection flag bit.
1 = Reset caused by PFD reset.
0 = PFD reset is not generated.
PFDEN
: Power-fail detection enable bit
1 = Enable PFD
0 = Disable PFD
R = Readable bit
W = Writable bit
ADDRESS ; 05
H
RESET VALUE : 1000_0000
FIGURE 12-14 POWER FAIL DETECTION SITUATIONS
Internal
RESET
V
DD
V
DD
=2.7V
V
DR
T
NVDD
≥
100nS
PFDEN = 1
PFDR
T
IRT
Internal
RESET
V
DD
V
DD
=2.7V
V
DR
PFDR
T
IRT
POR
PFDEN = 1
V
DD
≤
V
DR
When V
DD
falls below approximately 0.6V or 1.7V level, Power-On Reset may occur.
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