參數(shù)資料
型號(hào)： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁(yè)數(shù)： 43/59頁(yè)
文件大小： 660K
代理商： HMS77C2001
HMS77C2000/2001
40
Nov. 2002 Ver 1.1
before a WDT time-out occurs.
12.6.2 WDT PROGRAMMING CONSIDERATIONS
The
CLRWDT
instruction clears the WDT and the postscal-
er, if assigned to the WDT, and prevents it from timing out
and generating a device RESET.
The
SLEEP
instruction resets the WDT and the postscaler,
if assigned to the WDT. This gives the maximum SLEEP
time before a WDT wake-up reset.
Legend: Shaded boxes = Not used by WDT, - = unimplemented, read as ‘0’, u = unchanged.
12.7 TIME-OUT SEQUENCE, POWER DOWN,
AND WAKE-UP FROM SLEEP STATUS BITS
(TO/PD/UPWUF)
The TO, PD, and UPWUF bits in the STATUS register can
be tested to determine if a RESET condition has been
caused by a power-up , powe fail condition, a RESET,
Watchdog Timer (WDT) reset or SLEEP mode wake-up
reset.
FIGURE 12-10 WATCHDOG TIMER BLOCK DIAGRAM
Address
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Power-On
Reset
All other
resets
N/A
OPTION
GPWU
GPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
TABLE 12-6 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Postscaler
8
1
0
PSA
MUX
8 - to - 1 MUX
8-bit asynchronous
ripple counter
clear
MUX
PS2:PS0
PSA
1
0
WDT Time-Out
To TMR0
From TMR0 Clock Source
on-chip
RC-OSC
Watchdog Timer
enable
WDTE
SLEEP
clearing WDT
SLEEP
clearing WDT
PSA
UPWUF
TO
PD
RESET was caused by
0
1
1
Power-up (POR)
0
u
u
RESET or PFD reset from
normal operation
TABLE 12-7 TO/PD/UPWUF STATUS AFTER RESET
Legend: u = unchanged
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