參數(shù)資料
型號： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁數(shù)： 25/59頁
文件大?。?/td> 660K
代理商： HMS77C2001
HMS77C2000/2001
22
Nov. 2002 Ver 1.1
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the
OPTION
instruction, the contents of the
W register will be transferred to the OPTION register. A
RESET sets the OPTION<7:0> bits.
Note:
If TRIS bit is set to ‘0’, the wake-up on change and
pull-up functions are disabled for that pin; i.e., note
that TRIS overrides OPTION control of UPPU and
UPWU.
If the T0CS bit is set to ‘1’, UP2 is forced to be an
input even if TRIS UP2 = ‘0’.
FIGURE 9-6 OPTION REGISTER
UPWU
W
UPPU
W
T0CS
W
T0SE
W
PSA
W
PS2
W
PS1
W
PS0
W
bit7
6
bit0
5
4
3
2
1
UPWU
: Enable wake-up on pin change
(UP0, UP1, UP3)
1 = Disabled
0 = Enabled
UPPU
: Enable weak pull-ups (UP0, UP1, UP3)
1 = Disabled
0 = Enabled
T0CS
: Timer 0 clock source select bit
1 = Transition on EC0 pin
0 = Transition on internal instruction cycle,
F
OSC
/4
T0SE
: Timer 0 source edge select bit
1 = Increment on high to low transition
on EC0 pin
0 = Increment on low to high transition
on EC0 pin
PSA
: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to the Timer 0
PS2~PS0
: Prescaler rate select bits)
Bit Value
Timer 0 rate
WDT rate
000
1:2
1:1
001
1:4
1:2
010
1:8
1:4
011
1:16
1:8
100
1:32
1:16
101
1:64
1:32
110
1:128
1:64
111
1:256
1:128
W = Writable bit
-n = Value at POR reset
ADDRESS ; N/A
RESET VALUE : 1111_1111
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