參數(shù)資料
型號(hào)： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁數(shù)： 39/59頁
文件大?。?/td> 660K
代理商： HMS77C2001
HMS77C2000/2001
36
Nov. 2002 Ver 1.1
isters.
Legend: - = unimplemented, read as ‘0’, x = unknown, u = unchanged. q = value depends on condition.
Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged.
12.3.1 RESET ENABLE
This configuration bit when unprogrammed (left in the ‘1’
state) enables the external RESET function. When pro-
grammed, the RESET function is tied to the internal V
DD
,
and the pin is assigned to be a UPIO. See Figure 12-5.
When pin UP3/RESET/V
PP
is configured as RESET, the
Register
Address
Power-On Reset
RESET Reset
WDT time-out
Wake-up on Pin Change
W
N/A
qqqq xxxx
1
qqqq uuuu
INDF
00
H
xxxx xxxx
uuuu uuuu
TMR0
01
H
xxxx xxxx
uuuu uuuu
PC
02
H
1111 1111
1111 1111
STATUS
03
H
0001 1xxx
q00q quuu
2
FSR(HMS77C2000)
04
H
111x xxxx
111u uuuu
FSR(HMS77C2001)
04
H
110x xxxx
11uu uuuu
OSCCAL
05
H
1000 0000
uuuu uuu0
UPIO
06
H
--xx xxxx
--uu uuuu
OPTION
N/A
1111 1111
1111 1111
TRIS
N/A
--11 1111
--11 1111
TABLE 12-3 RESET CONDITIONS FOR ALL REGISTERS
1. Bits <7;2> of W register contain oscillator calibration values due to
MOVLW XX
instruction at top of memory.
2. See Table 12-7 for reset value for specific conditions.
If reset was due to wake-up on pin change, then bit7 = 1. All other resets will cause bit 7 = 0.
STATUS (Addr:03
H
)
PCL (Addr:02
H
)
Power On reset
0001 1xxx
1111 1111
RESET reset during normal operation
000u uuuu
1111 1111
RESET reset during SLEEP
0001 0uuu
1111 1111
WDT reset during SLEEP
0000 0uuu
1111 1111
WDT reset normal operation
0000 uuuu
1111 1111
Wake-up from SLEEP on pin change
1001 0uuu
1111 1111
TABLE 12-4 RESET CONDITIONS FOR SPECIAL REGISTER
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