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| 型號： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 44/59頁 |
| 文件大小： | 660K |
| 代理商： | HMS77C2001 |
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HMS77C2000/2001
Nov. 2002 Ver 1.1
41
Note:
The TO, PD, and UPWUF bits maintain their status
(u) until a reset occurs. A lowpulse on the RESET in-
put does not change the TO, PD, and UPWUF sta-
tus bits.
12.8 RESET ON BROWN-OUT
A brown-out is a condition where device power (V
DD
) dips
below its minimum value, but not to zero, and then recov-
ers. The device should be reset in the event of a brown-out.
To reset HMS77C2000 and HMS77C2001 when a brown-
out occurs, external brown-out protection circuits may be
built, as shown in Figure 12-11, Figure 12-12.
12.9 POWER-DOWN MODE (SLEEP)
A device may be powered down (SLEEP) and later pow-
ered up (Wake-up from SLEEP).
12.9.1 SLEEP
The Power-Down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but keeps
running, the TO bit (STATUS<4>) is set, the PD bit (STA-
TUS<3>) is cleared and the oscillator driver is turned off.
The I/O ports maintain the status they had before the
SLEEP
instruction was executed (driving high, driving
0
1
0
RESET Wake-up from
SLEEP
0
0
u
WDT time-out from normal
operation
0
0
0
WDT wake-up from SLEEP
1
1
0
Wake-up from SLEEP on pin
change
Event
UPWUF
TO
PD
Remarks
Power-up
0
1
1
WDT Time-
out
0
0
u
No effect on PD
SLEEP inst.
0
1
0
CLRWDT inst.
u
1
1
No effect on
UPUWF
TABLE 12-8 EFFECTS AFFECTION TO/PD/UPWUF
STATUS
Legend: u = unchanged
UPWUF
TO
PD
RESET was caused by
TABLE 12-7 TO/PD/UPWUF STATUS AFTER RESET
Legend: u = unchanged
FIGURE 12-11 BROWN-OUT PROTECTION CIRCUIT 1
FIGURE 12-12 BROWN-OUT PROTECTION CIRCUIT 2
33k
V
DD
10k
V
SS
Q1
40k
1
V
DD
RESET
This circuit will activate reset when V
DD
goes below
V
Z
+ 0.7V (wher V
Z
=Zener voltage).
V
DD
R1
V
DD
10k
V
SS
Q1
40k
1
V
DD
RESET
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when V
DD
is below a certain level such that:
R2
V
DD
V
DD
= R1/(R1+R2) = 0.7V
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