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| 型號： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 36/59頁 |
| 文件大小： | 660K |
| 代理商： | HMS77C2001 |
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HMS77C2000/2001
Nov. 2002 Ver 1.1
33
12. SPECIAL FEATURES OF THE CPU
What sets a microcontroller apart from other processors
are special circuits to deal with the needs of real-time ap-
plications. The HMS77C2000 and HMS77C2001 have a
host of such features intended to maximize system reliabil-
ity, minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection.
These features are:
- Oscillator selection
- Reset
- Power-On Reset (POR)
- Internal Reset Timer (IRT)
- Wake-up from SLEEP on pin change
- Watchdog Timer (WDT)
- SLEEP
- Code protection
- ID locations
- In-circuit Serial Programming
The HMS77C2000 and HMS77C2001 have a Watchdog
Timer which can be shut off only through configuration bit
WDTE. It runs off of its own RC oscillator for added reli-
ability. If using XT or LF selectable oscillator options,
there is always an 18 ms (nominal) delay provided by the
Internal
Reset Timer (IRT), intended to keep the chip in
reset until the crystal oscillator is stable. If using IRC or
ERC there is an 18 ms delay only on V
DD
power-up.
With this timer on-chip, most applications need no external
reset circuitry.
The SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through a change on input pins or through a Watchdog
Timer time-out. Several oscillator options are also made
available to allow the part to fit the application, including
an internal 4 MHz oscillator.
The ERC oscillator option saves system cost while the LF
crystal option saves power. A set of configuration bits are
used to select various options.
12.1 CONFIGURATION BITS
The HMS77C2000 and HMS77C2001 configuration word
consists of 12 bits. Configuration bits can be programmed
to select various device configurations. Two bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the RESET enable bit.
FIGURE 12-1 CONFIGURATION WORD FOR HMS77C2000/1
bit11
bit0
4
3
2
1
PORLS
: Power on reset level selection bit
1 = 1.7v(Typ.)
0 = Data retention voltage 0.6v(Typ.)
RESETE
: RESET pin enable bit.
1 = RESET pin enabled
0 = RESET tied to
V
DD
(internally).
CP
: Code protection bit.
1 = Code protection off
0 = Code protection on
WDTE
: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
FOSC1~FOSC0
: Oscillator selection bits
11 = ERC - external RC oscillator
10 = IRC - internal RC oscillator
01 = XT oscillator
00 = LF oscillator
Address
: FFF
H
CP
WDTE FOSC1 FOSC0
-
Unimplemented, read as ‘0’
Configuration Word
RESETE
PORLS
5
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