- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371862 > HMS77C2001 [General Purpose(2) : ADC/ LED/ SCI/ PWM] PDF資料下載
參數(shù)資料
| 型號： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 660K |
| 代理商： | HMS77C2001 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
HMS77C2000/2001
Nov. 2002 Ver 1.1
17
8.2 CLOCKING SCHEME/INSTRUCTION
CYCLE
The clock input (X
IN
pin) is internally divided by four to
generate four non-overlapping quadrature clocks namely
Q1, Q2, Q3 and Q4. Internally, the program counter is in-
cremented every Q1, and the instruction is fetched from
program memory and latched into instruction register in
Q4. It is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow is
shown in Figure 8-2 and Figure 8-3.
8.3 INSTRUCTION FLOW/PIPELINING
An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3
and Q4). The instruction fetch and execute are pipelined
such that fetch takes one instruction cycle while decode
and execute takes another instruction cycle. However, due
to the pipelining, each instruction effectively executes in
one cycle. If an instruction causes the program counter to
change (e.g.,
GOTO
) then two cycles are required to com-
plete the instruction (Figure 8-3).
A fetch cycle begins with the program counter (PC) incre-
menting in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3, and
Q4 cycles. Data memory is read during Q2 (operand read)
and written during Q4 (destination write).
FIGURE 8-2 CLOCK/INSTRUCTION CYCLE
Internal
Phase
clock
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Fetch INST(PC)
Execute INST(PC-1)
Fetch INST(PC+1)
Execute INST(PC)
Fetch INST(PC+2)
Execute INST(PC+1)
PC
PC+1
PC+2
PC
Q4
Q3
Q2
Q1
X
IN
FIGURE 8-3 INSTRUCTION PIPELINE FLOW
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline while the new instruction is being fetched and then executed.
1. MOVLW 03H
2. MOVWF UPIO
3. CALL SUB_1
4. BSF UPIO, BIT1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB 1
Execute SUB 1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMS81004 | REMOTE CONTROLLER |
| HMS81008 | siHYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| HMS81016 | REMOTE CONTROLLER |
| HMS81020ET | REMOTE CONTROLLER |
| HMS81024 | REMOTE CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMS81004 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REMOTE CONTROLLER |
| HMS81004E | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| HMS81008 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REMOTE CONTROLLER |
| HMS81008E | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:HYNIX SEMICONDUCTOR 8-BIT SINGLE-CHIP MICROCONTROLLERS |
| HMS81016 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:REMOTE CONTROLLER |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。