參數(shù)資料
型號(hào)： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁(yè)數(shù)： 40/59頁(yè)
文件大?。?/td> 660K
代理商： HMS77C2001
HMS77C2000/2001
Nov. 2002 Ver 1.1
37
internal pull-up is always on.
12.4 POWER-ON RESET (POR)
The HMS77C2000 and HMS77C2001 incorporate on-chip
Power-On Reset (POR) circuitry which provides an inter-
nal chip reset for most power-up situations.
The on-chip POR circuit holds the chip in reset until V
DD
has reached a high enough level for proper operation. To
take advantage of the internal POR, program the UP3/RE-
SET/V
PP
pin as RESET and tie through a resistor to V
DD
or program the pin as UP3. An internal weak pull-up resis-
tor is implemented using a transistor. This will eliminate
external RC components usually needed to create a Power-
on Reset. A maximum rise time for V
DD
is specified. See
‘Electrical Characteristics’ for details.
When the device starts normal operation (exits the reset
condition), device operating parameters (voltage, frequen-
cy, temperature, ...) must be met to ensure operation. If
these conditions are not met, the device must be held in re-
set until the operating parameters are met.
A simplified block diagram of the on-chip power-on reset
circuit is shown in Figure 12-6.
The power-on reset circuit and the internal reset timer cir-
cuit are closely related. On power-up, the reset latch is set
and the IRT is reset. The IRT timer begins counting once
it detects RESET to be high. After the time-out period,
which is typically 18 ms, it will reset the reset latch and
thus end the onchip reset signal.
A power-up example where RESET is held low is shown
in Figure 12-7. V
DD
is allowed to rise and stabilize before
bringing RESET high. The chip will actually come out of
reset T
IRT
msec after RESET goes high.
In Figure 12-8 and Figure 12-9, the on-chip power-on reset
feature is being used (RESET and V
DD
are tied together or
the pin is programmed to be UP3.). The V
DD
is stable be-
fore the start-up timer times out and there is no problem in
getting a proper reset.
And the user can select the level of power-on reset (0.6V,
1.7V).
Note:
When the device starts normal operation (exits the
reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be meet to
ensure operation. If these conditions are not met,
the device must be held in reset until the operating
conditions are met.
FIGURE 12-5 RESET SELECT
INTERNAL RESET
RESETE
WEAK
PULL-UP
UP3/RESET/V
PP
FIGURE 12-6 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
V
DD
Internal RESET
Power-Up
Detect
UP3/RESET/V
PP
pin
On-Chip
IRT OSC
reset
8-bit asynch ripple counter
(start-up timer)
S
R
Q
Q
wake-up on
pin change
pin change
SLEEP
RESETE
WDT time out
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