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HMS77C2000/2001
Nov. 2002 Ver 1.1
29
11. TIMER0 MODULE AND TMR0 REGISTER
The Timer0 module has the following features:
- 8-bit timer/counter register, TMR0
- Readable and writable
- 8-bit software programmable prescaler
- Internal or external clock select
- Edge select for external clock
Figure 11-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit (OP-
TION<5>). In timer mode, the Timer0 module will incre-
ment every instruction cycle (without prescaler). If TMR0
register is written, the increment is inhibited for the follow-
ing two instruction cycles (Figure 11-2 and Figure 11-3).
The user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting the T0CS bit (OP-
TION<5>). In this mode, Timer0 will increment either on
every rising or falling edge of pin T0CKI. The T0SE bit
(OPTION<4>) determines the source edge. Clearing the
T0SE bit selects the rising edge. Restrictions on the exter-
nal clock input are discussed in detail in Section 6.1.
The prescaler may be used by either the Timer0 module or
the Watchdog Timer, but not both. The prescaler assign-
ment is controlled in software by the control bit PSA (OP-
TION<3>). Clearing the PSA bit will assign the prescaler
to Timer0. The prescaler is not readable or writable. When
the prescaler is assigned to the Timer0 module, prescale
values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 de-
tails the operation of the prescaler.
A summary of registers associated with the Timer0 module
is found in Table 6-1.
FIGURE 11-1 TIMER0 BLOCK DIAGRAM
F
OSC
/4
1
UP2/EC0
pin
0
Sync with
Internal
Clocks
TMR0 reg
8
Data bus
(2 T
CY
delay)
T0SE
T0CS
1
MUX
0
1
MUX
PSA
1
PS
OUT
PS
OUT
Sync
Programmable
Prescaler
3
PS2, PS1, PS0
1
Note 1 : Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2 : The prescaler is shared with the watchdog timer.
Noise
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