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| 型號(hào)： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 34/59頁 |
| 文件大?。?/td> | 660K |
| 代理商： | HMS77C2001 |
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HMS77C2000/2001
Nov. 2002 Ver 1.1
31
a small RC delay of 20 ns). Refer to the electrical specifi-
cation of the desired device.
When a prescaler is used, the external clock input is divid-
ed by the asynchronous ripple counter-type prescaler so
that the prescaler output is symmetrical. For the external
clock to meet the sampling requirement, the ripple counter
must be taken into account. Therefore, it is necessary for
T0CKI to have a period of at least 4TOSC (and a small RC
delay of 40 ns) divided by the prescaler value. The only re-
quirement on T0CKI high and low time is that they do not
violate the minimum pulse width requirement of 10 ns. Re-
fer to parameters 40, 41 and 42 in the electrical specifica-
tion of the desired device.
11.1.2 TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the internal
clocks, there is a small delay from the time the external
clock edge occurs to the time the Timer0 module is actual-
ly incremented. Figure 11-4 shows the delay from the ex-
ternal clock edge to the timer incrementing.
11.1.3 OPTION REGISTER EFFECT ON UP2 TRIS
If the option register is set to read TIMER0 from the pin,
the port is forced to an input regardless of the TRIS register
setting.
11.2 PRESCALER
An 8-bit counter is available as a prescaler for the Timer0
module, or as a postscaler for the Watchdog Timer (WDT),
respectively. For simplicity, this counter is being referred
to as “prescaler” throughout this data sheet. Note that the
prescaler may be used by either the Timer0 module or the
WDT, but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for the
WDT, and vice-versa.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions writ-
ing to the TMR0 register (e.g.,
CLRF 1
,
MOVWF 1
,
BSF
1,x, etc.) will clear the prescaler. When assigned to WDT,
a
CLRWDT
instruction will clear the prescaler along with
the WDT. The prescaler is neither readable nor writable.
On a RESET, the prescaler contains all '0's.
11.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program execu-
tion). To avoid an unintended device RESET, the follow-
ing instruction sequence (Example 6-1) must be executed
when changing the prescaler assignment from Timer0 to
the WDT.
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0
→
WDT)
1.CLRWDT
2.CLRF TMR0
3.MOVLW ‘00xx1111’b ;These 3 lines (5,6,7)
4.OPTION
; are required only if
; desired
5.CLRWDT
;PS<2:0> are 000 or 001
6.MOVLW ‘00xx1xxx’b ;Set Postscaler to
7.OPTION
; desired WDT rate
To change prescaler from the WDT to the Timer0 module,
use the sequence shown in Example 6-2. This sequence
must be used even if the WDT is disabled. A
CLRWDT
in-
;Clear WDT
;Clear TMR0 & Prescaler
FIGURE 11-4 TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
T0+1
Note 1: Delay from clock input change to TMR0 increment is 3T
OSC
to 7T
OSC
. (Duration of Q = T
OSC
).
Therefore, the error in measuring the interval between two edges on TMR0 input =
±
4T
OSC
max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
Q1 Q2 Q3 Q4
T0+2
External Clock Input or
Prescaler Output
(2)
External Clock/Prescaler
Output After Sampling
Increment TMR0 (Q4)
TMR0
Small Pulse
misses sampling
(1)
(3)
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