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| 型號： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 19/59頁 |
| 文件大?。?/td> | 660K |
| 代理商： | HMS77C2001 |
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HMS77C2000/2001
16
Nov. 2002 Ver 1.1
8. ARCHITECTURAL OVERVIEW
8.1 CPU ARCHITECTURE
The GMS700 core is a RISC-based CPU and uses a modi-
fied Harvard architecture. This architecture uses two sepa-
rate memories with separate address buses, one for the
program memory and the other for the data memory. This
architecture adapts 33 single word instructions that are 12-
bit wide instruction and has an internal 2-stage pipeline
(fetch and execute), which results in execution of one in-
struction per single cycle(1uS@ 4MHz) except for pro-
gram branches.
The HMS77C2000 and HMS77C2001can address 0.5K/
1K x 12 Bits program memory and 25/41 Bytes data mem-
ory. And it can directly or indirectly address data memory.
The GMS700 core has three special function registers PC,
STATUS and FSR in data memory map and has ATU (Ad-
dress Translation Unit) to provide address for data memory
and has an 8-bit general purpose ALU and working regis-
ter(W) as an accumulator. The W register consists of 8-bit
register and it can not be an addressed register.
FIGURE 8-1 GMS700 CPU BLOCK DIAGRAM
Instruction
Decode
&
Control
Unit
STATUS
FSR
W
ALU
Instruction
Program Memory Address
Immediate Data
Data Bus
Data Memory Bus
Indirect Address
Address Translation
Unit
PC with 2-level Stack
Control
Signals
ALU
Status
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