參數(shù)資料
型號(hào)： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁數(shù)： 33/59頁
文件大?。?/td> 660K
代理商： HMS77C2001
HMS77C2000/2001
30
Nov. 2002 Ver 1.1
Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged.
11.1 USING TIMER0 WITH AN EXTERNAL
CLOCK
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock requirement
is due to internal phase clock (TOSC) synchronization. Al-
so, there is a delay in the actual incrementing of Timer0 af-
ter synchronization.
11.1.1 EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is the
same as the prescaler output. The synchronization of
T0CKI with the internal phase clocks is accomplished by
sampling the prescaler output on the Q2 and Q4 cycles of
the internal phase clocks (Figure 11-4). Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and a
small RC delay of 20 ns) and low for at least 2TOSC (and
FIGURE 11-2 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER 1:2
Address
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Power-On
Reset
RESET and
WDT Reset
01
H
TMR0
Timer0 - 8-bit real-time clock/counter
xxxx xxxx
uuuu uuuu
N/A
OPTION
UPWU
UPPU
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0011 1111
N/A
TRIS
-
-
UP5
UP4
UP3
UP2
UP1
UP0
--11 1111
--11 1111
TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0
[ W
’
TMR0 ]
PC-1
TMR0
Instruction
Fetch
Instruction
Executed
Q1 Q2 Q3 Q4
PC
Q1 Q2 Q3 Q4
PC+1
Q1 Q2 Q3 Q4
PC+2
Q1 Q2 Q3 Q4
PC+3
Q1 Q2 Q3 Q4
PC+4
Q1 Q2 Q3 Q4
PC+5
Q1 Q2 Q3 Q4
PC+6
Q1 Q2 Q3 Q4
[ TMR0
’
W ]
[ TMR0
’
W ]
[ TMR0
’
W ]
[ TMR0
’
W ]
[ TMR0
’
W ]
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0+1
Read TMR0
reads NT0+2
PC
(Program
Counter)
[ W
’
TMR0 ]
PC-1
TMR0
Instruction
Fetch
Instruction
Executed
Q1 Q2 Q3 Q4
PC
Q1 Q2 Q3 Q4
PC+1
Q1 Q2 Q3 Q4
PC+2
Q1 Q2 Q3 Q4
PC+3
Q1 Q2 Q3 Q4
PC+4
Q1 Q2 Q3 Q4
PC+5
Q1 Q2 Q3 Q4
PC+6
Q1 Q2 Q3 Q4
[ TMR0
’
W ]
[ TMR0
’
W ]
[ TMR0
’
W ]
[ TMR0
’
W ]
[ TMR0
’
W ]
T0
T0+1
NT0
NT0+1
PC
(Program
Counter)
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0+1
Read TMR0
reads NT0+2
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