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| 型號： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 45/59頁 |
| 文件大?。?/td> | 660K |
| 代理商： | HMS77C2001 |
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HMS77C2000/2001
42
Nov. 2002 Ver 1.1
low, or hi-impedance).
It should be noted that a RESET generated by a WDT time-
out does not drive the RESET pin low.
For lowest current consumption while powered down, the
T0CKI input should be at V
DD
or V
SS
and the UP3/RE-
SET/V
PP
pin must be at a logic high level (V
IHMC
) if RE-
SET is enabled.
12.9.2 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the
following events:
- An external reset input on UP3/RESET/V
PP
pin,
when configured as RESET.
- A Watchdog Timer time-out reset (if WDT was
enabled).
- A change on input pin UP0, UP1, or UP3/RE-
SET/V
PP
when wake-up on change is enabled.
These events cause a device reset. The TO, PD, and UP-
WUF bits can be used to determine the cause of device re-
set. The TO bit is cleared if a WDT time-out occurred (and
caused wake-up). The PD bit, which is set on power-up, is
cleared when SLEEP is invoked. The UPWUF bit indi-
cates a change in state while in SLEEP at pins UP0, UP1,
or UP3 (since the last time there was a file or bit operation
on UP port).
Note:
Right before entering SLEEP, read the input pins.
When in SLEEP, wake up occurs when the values
at the pins change from the state they were in at the
last reading. If a wake-up on change occurs and the
pins are not read before reentering SLEEP, a wake
up will occur immediately even if no pins change
while in SLEEP mode.
The WDT is cleared when the device wakes from sleep, re-
gardless of the wake-up source.
12.10 PROGRAM VERIFICATION/CODE PRO-
TECTION
If the code protection bit has not been programmed, the on-
chip program memory can be read out for verification pur-
poses.
The first 64 locations can be read by the HMS77C2000 and
HMS77C2001 regardless of the code protection bit setting.
The last memory location cannot be read if code protection
is enabled on the HMS77C2000 and HMS77C2001.
12.11 ID LOCATIONS
Four memory locations are designated as ID locations
where the user can store checksum or other code identifi-
cation numbers. These locations are not accessible during
normal execution but are readable and writable during pro-
gram/verify.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ‘0’s.
12.12 POWER FAIL DETECTION PROCES-
SOR
The HMS77C2000 and HMS77C2001 have an on-chip
power fail detection circuitry to immunize against power
noise. If V
DD
falls below a level for longer 100ns, the pow-
er fail detection processor may reset MCU to protect the
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