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HMS77C2000/2001
18
Nov. 2002 Ver 1.1
9. MEMORY ORGANIZATION
The HMS77C2000 and HMS77C2001 memories are orga-
nized into program memory and data memory. For devices
with more than 512 bytes of program memory, a paging
scheme is used. Program memory pages are accessed using
one STATUS register bit. For the HMS77C2001 with a
data memory register file of more than 32 registers, a bank-
ing scheme is used. Data memory banks are accessed using
the File Select Register (FSR).
9.1 PROGRAM MEMORY ORGANIZATION
The HMS77C2000 and HMS77C2001 devices have a 12-
bit program counter (PC) capable of addressing a 0.5K/1K
x 12 program memory space.
Only the first 512 x 12bits(0000
H
~01FF
H
) for the
HMS77C2000 and 1K x 12bits(0000
H
-03FF
H
) for the
HMS77C2001 are physically implemented. Refer to Fig-
ure 9-1, Figure 9-2. Accessing a location above these
boundaries will cause a wraparound within the first 512 x
12
space (HMS77C2000) or 1K
space(HMS77C2001). The effective reset vector is at
000
H
, (see Figure 9-1, Figure 9-2). Location 01FF
H
(HMS77C2000) or location 03FF
H
(HMS77C2001) con-
tains the internal clock oscillator calibration value. This
value should never be overwritten.
x 12
9.2 DATA MEMORY ORGANIZATION
Data memory is composed of registers, or bytes of RAM.
Therefore, data memory for a device is specified by its reg-
ister file. The register file is divided into two functional
groups: special function registers and general purpose reg-
isters.
The special function registers include the TMR0 register,
the program counter (PC), the status register, the I/O regis-
ters (ports), and the file select register (FSR). In addition,
special purpose registers are used to control the I/O port
configuration and prescaler options.
The general purpose registers are used for data and control
information under command of the instructions.
For the HMS77C2000 the register file is composed of 7
special function registers and 25 general purpose registers
(Figure 9-3).
For the HMS77C2001 the register file is composed of 7
special function registers, 25 general purpose registers, and
16 general purpose registers that may be addressed using a
banking scheme (Figure 9-4).
FIGURE 9-1 HMS77C2000 PROGRAM MEMORY MAP
AND STACK
PC<8:0>
Stack Level 1
Stack Level 2
Reset Vector
On-chip
Program
Memory
000
H
0FF
H
100
H
1FF
H
U
S
FIGURE 9-2 HMS77C2001 PROGRAM MEMORY MAP
AND STACK
PC<9:0>
Stack Level 1
Stack Level 2
Reset Vector
On-chip
Program
Memory
(Page 0)
000
H
0FF
H
100
H
3FF
H
U
S
On-chip
Program
Memory
(Page 1)
2FF
H
300
H
1FF
H
200
H