參數(shù)資料
型號(hào)： HMS77C2001
英文描述： [General Purpose(2) : ADC/ LED/ SCI/ PWM]
中文描述： [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制]
文件頁(yè)數(shù)： 42/59頁(yè)
文件大小： 660K
代理商： HMS77C2001
HMS77C2000/2001
Nov. 2002 Ver 1.1
39
12.5 INTERNAL RESET TIMER (IRT)
In the HMS77C2000 and HMS77C2001, IRT runs from
RESET and varies based on oscillator selection (see Table
8-5.)
The IRT operates on an internal RC oscillator. The proces-
sor is kept in RESET as long as the IRT is active. The IRT
delay allows V
DD
to rise above V
DD
min., and for the os-
cillator to stabilize.
Oscillator circuits based on crystals or ceramic resonators
require a certain time after power-up to establish a stable
oscillation. The on-chip IRT keeps the device in a RESET
condition for approximately 18ms after RESET has
reached a logic high (V
IH
RESET) level. Thus, program-
ming UP3/RESET/V
PP
as RESET and using an external
RC network connected to the RESET input is not required
in most cases, allowing for savings in cost-sensitive and/or
space restricted applications, as well as allowing the use of
the UP3/RESET/V
PP
pin as a general purpose input.
The Device Reset time delay will vary from chip to chip
due to V
DD
, temperature, and process variation. See AC
parameters for details.
The IRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications us-
ing the WDT to wake from SLEEP mode automatically.
12.6 WATCHDOG TIMER (WDT)
The Watchdog Timer (WDT) is a free running on-chip RC
oscillator which does not require any external components.
This RC oscillator is separate from the external RC oscil-
lator of the UP5/X
IN
pin and the internal 4 MHz oscillator.
That means that the WDT will run even if the main proces-
sor clock has been stopped, for example, by execution of a
SLEEP
instruction. During normal operation or SLEEP, a
WDT reset or wake-up reset generates a device RESET.
The TO bit (STATUS<4>) will be cleared upon a Watch-
dog Timer reset. The WDT can be permanently disabled
by programming the configuration bit WDTE as a ‘0’ (Sec-
tion 8.1). Refer to the HMS77C2000 and HMS77C2001
Programming Specifications to determine how to access
the configuration word.
12.6.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a pres-
caler with a division ratio of up to 1:128 can be assigned to
the WDT (under software control) by writing to the OP-
TION register. Thus, a time-out period of a nominal 2.3
seconds can be realized. These periods vary with tempera-
ture, V
DD
and part-to-part process variations (see DC
specs).
Under worst case conditions (V
DD
= Min., Temperature =
Max., max. WDT prescaler), it may take several seconds
FIGURE 12-9 TIME-OUT SEQUENCE ON POWER-UP(RESET TIED TO V
DD
): SLOW V
DD
RISE TIME
V
DD
RESET
INTERNAL POR
IRT TIMER-OUT
INTERNAL RESET
T
IRT
Oscillator
Configuration
POR Reset
Subsequent
Resets
IRC & ERC
18 ms(typ.)
300us(typ.)
XT & LF
18 ms(typ.)
18ms(typ.)
TABLE 12-5 IRT(INTERNAL RESET TIMER PERIOD)
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