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| 型號： | HMS77C2001 |
| 英文描述： | [General Purpose(2) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（2）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 26/59頁 |
| 文件大?。?/td> | 660K |
| 代理商： | HMS77C2001 |
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HMS77C2000/2001
Nov. 2002 Ver 1.1
23
9.5 OSCCAL REGISTER
The oscillator calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains five bits
for calibration. Increasing the cal value increases the fre-
quency.
Also it controls power fail detection circuit by the lower
2bits.
9.6 PROGRAM COUNTER
As a program instruction is executed, the program counter
(PC) will contain the address of the next program instruc-
tion to be executed. The PC value is increased by one every
instruction cycle, unless an instruction changes the PC.
For a
GOTO
instruction, bits 8~0 of the PC are provided
by the
GOTO
instruction word. The PC Latch (PCL) is
mapped to PC<7~0>. Bit 5 of the STATUS register pro-
vides page information to bit 9 of the PC (Figure 9-8).
For a
CALL
instruction, or any instruction where the PCL
is the destination, bits 7~0 of the PC again are provided by
the instruction word. However, PC<8> does not come
from the instruction word, but is always cleared (Figure 9-
8).
Instructions where the PCL is the destination, or Modify
PCL instructions, include
MOVWF PC, ADDWF PC,
and
BSF PC,5.
Note:
Because PC<8> is cleared in the
CALL
instruction,
or any Modify PCL instruction, all subroutine calls or
computed jumps are limited to the first 256 locations
of any program memory page (512 words long).
FIGURE 9-7 OSCCAL REGISTER
CAL4
R/W
CAL3
R/W
CAL2
R/W
CAL1
R/W
CAL0
R/W
-
R/W
PFDF
R/W
PFDEN
R/W
bit7
6
bit0
5
4
3
2
1
CAL4~CAL0
: Calibration Bits
11111 = High frequency
10000 = Middle frequency
00000 = Low frequency
PFDF
: Power-fail detection flag bit.
1 = Reset caused by PFD reset.
0 = PFD reset is not generated.
PFDEN
: Power-fail detection enable bit
1 = Enable PFD
0 = Disable PFD
R = Readable bit
W = Writable bit
ADDRESS ; 05
H
RESET VALUE : 1000_0000
GOTO
Instruction
CALL
or Modify PCL Instruction
FIGURE 9-8 LOADING OF PC BRANCH INSTRUCTION
PCL
PC
7
0
Instruction Word
8
9
10
11
7
0
PA0
STATUS
Reset to ‘0’
PCL
PC
7
0
Instruction Word
8
9
10
11
7
0
STATUS
PA0
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