參數(shù)資料
型號: DSP1628
英文描述: TVS 400W 60V BIDIRECT SMA
中文描述: 澄清,串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù): 89/114頁
文件大?。?/td> 804K
代理商: DSP1628
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
87
Lucent Technologies Inc.
10 Timing Characteristics for 2.7 V Operation
(continued)
10.1 DSP Clock Generation
* See Table 62 for input clock electrical requirements.
Free-running clock.
Wait-stated clock (see Table 38).
§ W = number of wait-states.
Figure 11. I/O Clock Timing Diagram
* Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.
Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.
* T = internal clock period, set by CKI or by CKI and the PLL parameters.
Table 66. Timing Requirements for Input Clock
Abbreviated Reference
Parameter
19.2 ns and 12.5 ns
*
Min
Max
20
10
10
Unit
ns
ns
ns
t1
t2
t3
Clock In Period (high to high)
Clock In Low Time (low to high)
Clock In High Time (high to low)
Table 67. Timing Characteristics for Input Clock and Output Clock
Abbreviated Reference
Parameter
19.2 ns
12.5 ns
Unit
Min
Max
Min
Max
t4
Clock Out High Delay
14
10
ns
t5
Clock Out Low Delay (high to low)
14
10
ns
t6
Clock Out Period (low to low)
T*
T*
ns
t6a
Clock Out Period with SLOWCKI Bit
Set in powerc Register (low to low)
0.74
3.8
0.74
3.8
μ
s
t4
t6, t6a
t1
t2
1X CKI*
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
t5
CKO
EXTERNAL MEMORY CYCLE
W = 1
§
CKO
t3
5-4009 (C).a
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