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參數資料
| 型號： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數： | 74/114頁 |
| 文件大小： | 804K |
| 代理商： | DSP1628 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
72
Lucent Technologies Inc.
6 Signal Descriptions
Figure 12. DSP1628 Pinout by Interface
EXTERNAL
MEMORY
INTERFACE
IO
ERAMHI
EROM
EXM
AB[15:0]
DB[15:0]
RWN
SYSTEM
INTERFACE
OR
CONTROL I/O
INTERFACE
OBE1
DI1
OLD1
OCK1
DO1
TDI
TDO
TCK
TMS
PODS OR OLD2
PSTAT OR DO2
PCSN OR OCK2
POBE OR OBE2
PBSEL OR SYNC2
PB2 OR DOEN2
PIBF OR IBF2
PIDS OR ILD2
PB1 OR DI2
PB0 OR ICK2
PB3 OR SADD2
PB[7:4] OR IOBIT[3:O]
DSP1628
RSTB
CKO
CKI2
CKI
IACK
TRAP
STOP
INT[1:0]
VEC[3:0] OR IOBIT[4:7]
PARALLEL HOST
INTERFACE
OR
SERIAL INTERFACE #2
AND CONTROL I/O
INTERFACE
ILD1
ICK1
IBF1
SERIAL
INTERFACE #1
SYNC1
ERAMLO
SADD1
DOEN1
JTAG TEST
INTERFACE
2
4
16
16
4
TRST
DSEL
5-4006 (C).h
Figure 12 shows the pinout for the DSP1628. The sig-
nals can be separated into five interfaces as shown.
These interfaces and the signals that comprise them
are described below.
6.1 System Interface
The system interface consists of the clock, interrupt,
and reset signals for the processor.
RSTB
Reset:
Negative assertion. A high-to-low transition
causes the processor to enter the reset state. The
auc
,
powerc
,
sioc
,
sioc2
,
phifc
,
pdx0
,
tdms
,
tdms2
,
tim-
erc
,
timer0
,
sbit
(upper byte),
inc
,
ins
(except OBE,
OBE2, and PODS status bits set),
alf
(upper 2 bits,
AWAIT and LOWPR),
ioc
,
rb
, and
re
registers are
cleared. The
mwait
register is initialized to all 0s (zero
wait-states) unless the EXM pin is high and the INT1 pin
is low. In that case, the
mwait
register is initialized to all
1s (15 wait-states).
Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2.
The DAU condition flags are not affected by reset.
IOBIT[7:0] are initialized as inputs. If any of the IOBIT
pins are switched to outputs (by writing
sbit
), their initial
value will be logic zero (see Figure 44, Register Settings
After Reset).
Upon negation of the signal, the processor begins exe-
cution at location 0x0000 in the active memory map
(see Section 4.4, Memory Maps and Wait-States).
CKI
Input Clock:
A mask-programmable option selects one
of three possible input buffers for the CKI pin (see Sec-
tion 7, Mask-Programmable Options, and Table 1, Pin
Descriptions). The internal CKI from the output of the
selected input buffer can then drive the internal proces-
sor clock directly (1X) or drive the on-chip PLL (see
Section 4.13). The PLL allows the CKI input clock to be
at a lower frequency than the internal processor clock.
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