- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377000 > DSP1628 TVS 400W 60V BIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號(hào)： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 87/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)當(dāng)前第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
85
Lucent Technologies Inc.
9 Electrical Characteristics and Requirements
(continued)
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
t
L
= PLL lock time (see Table 64).
The power dissipation listed is for internal power dissipation only. Total power dissipation can be calculated on the
basis of the application by adding C x V
DD
2
x f for each output, where C is the additional load capacitance and f is
the output frequency.
Power dissipation due to the input buffers is highly dependent on the input voltage level. At full CMOS levels, es-
sentially no dc current is drawn. However, for levels between the power supply rails, especially at or near the thresh-
old of V
DD
/2, high currents can flow. Although input and I/O buffers may be left untied (since the input voltage levels
of the input and I/O buffers are designed to remain at full CMOS levels when not driven by the DSP), it is still rec-
ommended that unused input and I/O pins be tied to V
SS
or V
DD
through a 10 k
resistor to avoid application am-
biguities. Further, if I/O pins are tied high or low, they should be pulled fully to V
SS
or V
DD
.
WARNING: The device needs to be clocked for at least six CKI cycles during reset after powerup. Other-
wise, high currents may flow.
Table 65. Power Dissipation and Wake-Up Latency
(continued)
Operating Mode
(Unused inputs at V
DD
or V
SS)
Typical Power Dissipation (mW)
Wake-Up Latency
V
DD=
3 V
3 V
3 V
3 V
I/O Units ON, ECCP OFF
powerc[7:4,0] = 0x01
I/O Units OFF, ECCP OFF
powerc[7:4,0] = 0xF1
(PLL Not Used
During Wake State)
(PLL Used
During Wake State)
Sleep with Slow Internal Clock
Small Signal Disabled
powerc[15:14] = 11,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
Small Signal
0.40
0.30
20
μ
s
20
μ
s + t
L
Software Stop
powerc[15:12] = 0011
PLL Disabled During STOP
CMOS
0.060
0.060
3T*
3T* + t
L
Software Stop
powerc[15:12] = 1111
PLL Disabled During STOP
Small Signal
0.060
0.060
20
μ
s
20
μ
s + t
L
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Disabled During STOP
CMOS
0.060
1.20
0.060
1.20
3T*
3T*
—
—
Small Signal
Hardware Stop (STOP = V
SS
)
powerc[15:12] = 0000
PLL Enabled During STOP
CMOS
2.5
3.6
2.5
3.6
3T*
3T*
3T*
3T*
Small Signal
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP16210 | TVS 400W 6.5V UNIDIRECT SMA |
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
| DSP16410 | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP1629 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1629 Digital Signal Processor |
| DSP1629BA10K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|BGA|144PIN|PLASTIC |
| DSP1629BA10K12.5IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1629BA10K16.7IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|BGA|144PIN|PLASTIC |
| DSP1629BA10K19.2IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。