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參數(shù)資料
| 型號(hào)： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 73/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
71
5 Software Architecture
(continued)
N Field
Number of instructions to be loaded into the cache. Zero
implies redo operation.
K Field
Number of times the N instructions in cache are to be
executed. Zero specifies use of value in
cloop
register.
JA Field
12-bit jump address.
R/W Field
A zero specifies a write, *(OFFSET) = DR.
A one specifies a read, DR = *(OFFSET).
Table 60. F3 Field
Table 61. SRC2 Field
Note: xx encodes the auxiliary register to be used; 00 (
ar0
),
01(
ar1
), 10 (
ar2
), or 11(
ar3
).
Specifies the operation in an F3 ALU instruction.
F3
1000
1001
1010
1011
1101
1110
1111
Operation
aD = aS[h, l]
aD = aS[h, l]
aS[h, l]
aS[h, l]
aD = aS[h, l]
aD = aS[h, l]
aD = aS[h, l]
|
^
&
–
+
&
–
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
{aT, IM16, p}
Specifies operands in an F3 ALU instruction.
SRC2
00
10
01
11
Operands
aSl, IM16
aSh, IM16
aS, aT
aS, p
Table 62. BMU Encodings
F4
0000
0001
0000
0001
1000
1001
1000
1001
1100
1101
1100
1101
0000
0001
1110
0010
1110
0010
1110
1010
0111
0111
AR
00xx
00xx
10xx
10xx
0000
0000
1000
1000
0000
0000
1000
1000
1100
11xx
0000
00xx
0100
01xx
1000
10xx
0000
0001
Operation
aD = aS >> arM
aD = aS << arM
aD = aS >>> arM
aD = aS <<< arM
aD = aS >> aS
aD = aS << aS
aD = aS >>> aS
aD = aS <<< aS
aD = aS >> IM16
aD = aS << IM16
aD = aS >>> IM16
aD = aS <<< IM16
aD = exp(aS)
aD = norm(aS, arM)
aD = extracts(aS, IM16)
aD = extracts(aS, arM)
aD = extractz(aS, IM16)
aD = extractz(aS, arM)
aD = insert(aS, IM16)
aD = insert(aS, arM)
aD = aS:aa0
aD = aS:aa1
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