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參數資料
| 型號： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數： | 78/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
76
Lucent Technologies Inc.
6 Signal Descriptions
(continued)
6.4 Parallel Host Interface or Serial
Interface #2 and Control I/O Interface
This interface pin multiplexes a parallel host interface
with a second serial I/O interface and a 4-bit I/O inter-
face. The interface selection is made by writing the
ESIO2 bit in the
ioc
register (see Table 42 and
Section 4.1). The functions and signals for the second
SIO correspond exactly with those in SIO #1. Therefore,
the pin descriptions below discuss only PHIF and BIO
pin functionality.
PB[7:0]
Parallel I/O Data Bus:
This 8-bit bidirectional bus is
used to input data to, or output data from, the PHIF.
Note that PB[3:0] are pin multiplexed with SIO2 func-
tionality, and PB[7:4] are pin multiplexed with BIO unit
pins IOBIT[3:0] (see Section 4.1).
PCSN
Peripheral Chip Select Not:
Negative assertion.
PCSN is an input. While PCSN is low, the data strobes
PIDS and PODS are enabled. While PCSN is high, the
DSP1628 ignores any activity on PIDS and PODS.
PBSEL
Peripheral Byte Select:
An input pin, configurable in
software. Selects the high or low byte of
pdx0
available
for host accesses.
PSTAT
Peripheral Status Select:
PSTAT is an input. When a
logic 0, the PHIF will output the
pdx0
[out] register on
the PB bus. When a logic 1, the PHIF will output the
contents of the PSTAT register on PB[7:0].
PIDS
Parallel Input Data Strobe:
An input pin, software con-
figurable to support both Inteland Motorolaprotocols.
In Intelmode: Negative assertion. PIDS is pulled low by
an external device to indicate that data is available on
the PB bus. The DSP latches data on the PB bus on the
rising edge (low-to-high transition) of PIDS or PCSN,
whichever comes first.
In Motorolamode: PIDS/PRWN functions as a read/
write strobe. The external device sets PIDS/PRWN to a
logic 0 to indicate that data is available on the PB bus
(write operation by the external device). A logic 1 on
PIDS/PRWN indicates an external read operation by
the external device.
PODS
Parallel Output Data Strobe:
An input pin, software
configurable to support both Inteland Motorolaproto-
cols.
In Intelmode: Negative assertion. When PODS is
pulled low by an external device, the DSP1628 places
the contents of the parallel output register,
pdx0
, onto
the PB bus.
In Motorolamode: Software-configurable assertion
level. The external device uses PODS/PDS as its data
strobe for both read and write operations.
PIBF
Parallel Input Buffer Full:
An output pin with positive
assertion; configurable in software. This flag is cleared
after reset, indicating an empty input buffer
pdx0
[in].
PIBF is set immediately after the rising edge of PIDS or
PCSN, indicating that data has been latched into the
pdx0
[in] register. When the DSP1628 reads the con-
tents of this register, emptying the buffer, the flag is
cleared.
Configured in software, PIBF may become the logical
OR of the PIBF and POBE flags.
POBE
Parallel Output Buffer Empty:
An output pin with pos-
itive assertion; configurable in software. This flag is set
after reset, indicating an empty output buffer
pdx0
[out].
POBE is set immediately after the rising edge of PODS
or PCSN, indicating that the data in
pdx0
[out] has been
driven onto the PB bus. When the DSP1628 writes to
pdx0
[out], filling the buffer, this flag is cleared.
6.5 Control I/O Interface
This interface is used for status and control operations
provided by the bit I/O unit of the DSP1628. It is pin mul-
tiplexed with the PHIF and VEC[3:0] pins (see Section
4.1). Setting the ESIO2 and EBIOH bits in the
ioc
reg-
ister provides a full 8-bit BIO interface at the associated
pins.
IOBIT[7:0]
I/O Bits [7:0]:
Each of these bits can
be independently
configured as either an input or an output. As outputs,
they can be independently set, toggled, or cleared. As
inputs, they can be tested independently or in combina-
tions for various data patterns.
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