參數(shù)資料
型號: DSP1628
英文描述: TVS 400W 60V BIDIRECT SMA
中文描述: 澄清,串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù): 107/114頁
文件大?。?/td> 804K
代理商: DSP1628
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
105
Lucent Technologies Inc.
10 Timing Characteristics for 2.7 V Operation
(continued)
* See
sioc
register, MSB field, to determine if B0 is the MSB or LSB. See
sioc
register, ILEN field, to determine if the DO word length
is 8 bits or 16 bits.
Figure 31. SIO Passive Mode Output Timing Diagram
For multiprocessor mode, see note in Section 10.10.
Device is fully static; t80 is tested at 200 ns.
Table 100. Timing Requirements for Serial Inputs
Abbreviated Reference
Parameter
Min
Max
Unit
t80
Clock Period (high to high)
Clock Low Time (low to high)
Clock High Time (high to low)
Load High Setup (high to high)
Load Low Setup (low to high)
Load Hold (high to invalid)
40
ns
t81
t82
t83
t84
t85
18
18
8
8
0
ns
ns
ns
ns
ns
Table 101. Timing Characteristics for Serial Outputs
Abbreviated Reference
t87
t88
t89
t90
t92
t93
t94
t95
t96
Parameter
Min
3
3
Max
35
35
35
35
35
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Delay (high to valid)
Enable Data Delay (low to active)
Disable Data Delay (high to 3-state)
Data Hold (high to invalid)
Address Delay (high to valid)
Address Hold (high to invalid)
Enable Delay (low to active)
Disable Delay (high to 3-state)
OBE Delay (high to high)
DOEN
V
IH
V
IL
SADD
V
OH
V
OL
OLD
V
IH
V
IL
OCK
V
IH
V
IL
t85
t80
t81
t82
t84
t83
t85
t88
B0
B1
B7
BN – 1
t90
t90
t87
t94
AD0
AD1
AD7
t93
t93
t92
AS7
t89
t95
OBE
V
OH
V
OL
DO*
V
OH
V
OL
t96
5-4796 (F)
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