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參數(shù)資料
| 型號(hào)： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說(shuō)明 |
| 文件頁(yè)數(shù)： | 79/114頁(yè) |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
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Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
77
6 Signal Descriptions
(continued)
6.6 JTAG Test Interface
The JTAG test interface has features that allow pro-
grams and data to be downloaded into the DSP via four
pins. This provides extensive test and diagnostic capa-
bility. In addition, internal circuitry allows the device to
be controlled through the JTAG port to provide on-chip
in-circuit emulation. Lucent Technologies provides
hardware and software tools to interface to the on-chip
HDS via the JTAG port.
Note:
The DSP1628 provides all JTAG/IEEE1149.1
standard test capabilities including boundary
scan. See the DSP1611/17/18/27 Digital Signal
Processor Information Manualfor additional in-
formation on the JTAG test interface.
TDI
Test Data Input:
JTAG serial input signal. All serial-
scanned data and instructions are input on this pin. This
pin has an internal pull-up resistor.
TDO
Test Data Output:
JTAG serial output signal. Serial-
scanned data and status bits are output on this pin.
TMS
Test Mode Select:
JTAG mode control signal that,
when combined with TCK, controls the scan operations.
This pin has an internal pull-up resistor.
TCK
Test Clock:
JTAG serial shift clock. This signal clocks
all data into the port through TDI, and out of the port
through TDO, and controls the port by latching the TMS
signal inside the state-machine controller.
TRST
Test Reset:
Negative assertion. JTAG test reset. When
asserted low, asynchronously resets JTAG TAP con-
troller. In an application environment, this pin must be
asserted prior to or concurrent with RSTB. This pin has
an internal pull-up resistor.
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