參數(shù)資料
型號(hào)： DSP1628
英文描述： TVS 400W 60V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說明
文件頁數(shù)： 65/114頁
文件大?。?/td> 804K
代理商： DSP1628
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
63
5 Software Architecture
(continued)
* The field definitions for the
ioc
register are different from the DSP1610.
1. The phase of CKI is synchronized by the rising edge of RSTB.
2. When SLOWCKI is enabled in the
powerc
register, these options reflect the low-speed internal ring oscillator.
3. The wait-stated clock reflects the internal instruction cycle and may be stretched based on the
mwait
register setting (see Table 40).
During sequenced external memory accesses, it completes one cycle.
4. The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based
on the
mwait
register setting (see Table 40).
Table 42. ioc Register*
Bit
Field
Reserved EXTROM CKO2
15
14
13
12
11
10
9
8—7
CKO[1:0]
6—4
3—0
EBIOH
WEROM
ESIO2
SIOLBC
Reserved DENB[3:0]
ioc Fields
ioc Field
EXTROM
CKO2
EBIOH
WEROM
ESIO2
SIOLBC
CKO[1:0]
DENB3
DENB2
DENB1
DENB0
Description
If 1, sets AB15 low during external memory accesses when WEROM = 1.
CKO configuration (see below).
If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins.
If 1, allows writing into external program (X) memory.
If 1, enables SIO2 and low half of BIO, and disables PHIF from pins.
If 1, DO1 and DO2 looped back to DI1 and DI2.
CKO configuration (see below).
If 1, delay EROM.
If 1, delay ERAMHI.
If 1, delay IO.
If 1, delay ERAMLO.
CKO2
—
0
0
0
0
1
1
1
1
CKO1
—
0
0
1
1
0
0
1
1
CKO0
—
0
1
0
1
0
1
0
1
CKO Output
Description
—
1X
CKI
PLL
CKI x M/(2N)
CKI x (M/(2N)) / [1 + W] Wait-stated clock.
1—3
1
0
CKI
CKI x (M/(2N)) / [1 + W] Sequenced, wait-stated clock.
1—4
Reserved
Reserved
Free-running clock.
1, 2
CKI/(1 + W)
1
0
CKI
CKI/(1 + W)
Held high.
Held low.
Output of CKI buffer.
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