參數(shù)資料
型號： DSP1628
英文描述： TVS 400W 60V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù)： 49/114頁
文件大?。?/td> 804K
代理商： DSP1628
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
47
5 Software Architecture
(continued)
A single-cycle squaring function is provided in DSP1628. By setting the X = Y = bit in the
auc
register, any instruction
that loads the high half of the
y
register also loads the
x
register with the same value. A subsequent instruction to
multiply the
x
register and
y
register results in the square of the value being placed in the
p
register. The instruction
a0
=
p
p
=
x
*
y
y
= *
r0
++ with the X = Y = bit set to one will read the value pointed to by
r0
, load it to both
x
and
y
, multiply the previously fetched value of
x
and
y
, and transfer the previous product to
a0
. A table of values pointed
to by
r0
can thus be squared in a pipeline with one instruction cycle per each value. Multiply/ALU instructions that
use
x
= X transfer statements (such as
a0
=
p
p
=
x
*
y
y
= *
r0
++
x
=
*pt
++) are not recommended for squaring
because
pt
will be incremented even though
x
is not loaded from the value pointed to by
pt
. Also, the same conflict
wait occurrences from reading the same bank of internal memory or reading from external memory apply, since the
X space fetch occurs (even though its value is not used).
The l in [ ] is an optional argument that specifies the low 16 bits of
aT
or
y
.
Add cycles for:
1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.
2. If an X space access and a Y space access are made to the same bank of DPRAM in one instruction, add one cycle.
Note: For transfer statements when loading the upper half of an accumulator, the lower half is cleared if the corresponding CLR bit in the
auc
register is zero.
auc
is cleared by reset.
Table 17. Multiply/ALU Instructions
Function Statement
Transfer Statement
y = Y
y = aT
y[l] = Y
aT[l] = Y
x = Y
Y
Y = y[l]
Y = aT[l]
Z:y
Z:y[l]
Z:aT[l]
Cycles (Out/In Cache)
2/1
2/1
1/1
1/1
1/1
1/1
2/2
2/2
2/2
2/2
2/2
p = x * y
p = x * y
p = x * y
p = x * y
x = X
x = X
aD = p
aD = aS + p
aD = aS – p
aD = p
aD = aS + p
aD = aS – p
aD = y
aD = aS + y
aD = aS – y
aD = aS & y
aD = aS | y
aD = aS ^ y
aS – y
aS & y
x = X
Table 18. Replacement Table for Multiply/ALU Instructions
Replace
aD, aS, aT
X
Value
Meaning
a0, a1
*pt++, *pt++i
One of two DAU accumulators.
X memory space location pointed to by
pt
.
pt
is postmodified by +1
and i, respectively.
RAM location pointed to by
rM
(M = 0, 1, 2, 3).
rM
is postmodified by
0, +1, –1, or j, respectively.
Read/Write compound addressing.
rM
(M = 0, 1, 2, 3) is used twice.
First, postmodified by 0, +1, –1, or j, respectively; and, second, post-
modified by +1, 0, +2, or k, respectively.
Y
*rM, *rM++, *rM--, rM++j
Z
*rMzp, *rMpz, *rMm2, *rMjk
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