參數(shù)資料
型號(hào)： DSP1628
英文描述： TVS 400W 60V BIDIRECT SMA
中文描述： 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊(cè)說明
文件頁數(shù)： 102/114頁
文件大小： 804K
代理商： DSP1628
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
100
10 Timing Characteristics for 2.7 V Operation
(continued)
Figure 25. PHIF MotorolaMode Signaling (Pulse Period and Flags) Timing Diagram
* An input/output transaction is initiated by PCSN or PDS going low, whichever comes last. For example, t53 and t54 should be referenced
to PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first.
All requirements referenced to PCSN should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or
complete a transaction.
PDS is programmable to be active-high or active-low. It is shown active-low in Figures 24 and 25. POBE and PIBF may be programmed to
be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown.
Table 90. Timing Characteristics for PHIF MotorolaMode Signaling
Abbreviated Reference
t53*
Parameter
Min
—
Max
17
Unit
ns
PCSN/PDS
to POBE
(high to high)
PCSN/PDS
to PIBF
(high to high)
t54*
—
17
ns
Table 91. Timing Requirements for PHIF MotorolaMode Signaling
Abbreviated Reference
Parameter
Min
Max
Unit
t55
PCSN/PDS/PRWN Pulse Width (high to low)
20
—
ns
t56
PCSN/PDS/PRWN Pulse Width (low to high)
20
—
ns
PODS
PIDS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t55
t56
t55
t56
t55
t56
PCSN
t53
t54
16-bit READ
8-bit WRITE
PBSEL
POBE
PIBF
t54
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
t56
t56
t55
t53
8-bit READ
16-bit WRITE
5-4039 (C).a
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