- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377000 > DSP1628 TVS 400W 60V BIDIRECT SMA PDF資料下載
參數(shù)資料
| 型號： | DSP1628 |
| 英文描述： | TVS 400W 60V BIDIRECT SMA |
| 中文描述： | 澄清，串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明 |
| 文件頁數(shù)： | 38/114頁 |
| 文件大?。?/td> | 804K |
| 代理商： | DSP1628 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
36
Lucent Technologies Inc.
4 Hardware Architecture
(continued)
4.13 Clock Synthesis
Figure 10. Clock Source Block Diagram
powerc
RING
OSCILLATOR
M
U
X
÷
2
÷
N
PHASE
DETECTOR
CHARGE
PUMP
VCO
VCO CLOCK
f
VCO
LOOP
FILTER
÷
M
LF[3:0]
Mbits[4:0]
Nbits[2:0]
PLL/SYNTHESIZER
CKI INPUT CLOCK
LOCK
(FLAG TO INDICATE LOCK
CONDITION OF PLL)
f
CKI
f
SLOW CLOCK
SLOWCKI
pllc
PLLEN
INTERNAL
PROCESSOR
CLOCK
f
INTERNAL CLOCK
PLLSEL
f
CKI
5-4520 (F)
The DSP1628 provides an on-chip, programmable
clock synthesizer. Figure 10 is the clock source dia-
gram. The 1X CKI input clock, the output of the synthe-
sizer, or a slow internal ring oscillator can be used as
the source for the internal DSP clock. The clock synthe-
sizer is based on a phase-locked loop (PLL), and the
terms clock synthesizer and PLL are used interchange-
ably.
On powerup, CKI is used as the clock source for the
DSP. This clock is used to generate the internal proces-
sor clocks and CKO, where f
CKI
= f
CKO
. Setting the ap-
propriate bits in the
pllc
control register (described in
Table 36) will enable the clock synthesizer to become
the clock source. The
powerc
register, which is dis-
cussed in Section 4.14, can override the selection to
stop clocks or force the use of the slow clock for low-
power operation.
PLL Control Signals
The input to the PLL comes from one of the three mask-
programmable clock options: CMOS, or small-signal.
The PLL cannot operate without an external input clock.
To use the PLL, the PLL must first be allowed to stabi-
lize and lock to the programmed frequency. After the
PLL has locked, the LOCK flag is set and the lock detect
circuitry is disabled. The synthesizer can then be used
as the clock source. Setting the PLLSEL bit in the
pllc
register will switch sources from f
CKI
to f
VCO
/2 without
glitching. It is important to note that the setting of the
pllc
register must be maintained. Otherwise, the PLL
will seek the new set point. Every time the
pllc
register
is written, the LOCK flag is reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP16210 | TVS 400W 6.5V UNIDIRECT SMA |
| DSP1627 | TVS 400W 6.5V BIDIRECT SMA |
| DSP1629 | TVS 400W 64V UNIDIRECT SMA |
| DSP16410C | TVS 400W 7.0V UNIDIRECT SMA |
| DSP16410 | 16-bit fixed point DSP with Flash |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP1629 | 制造商:AGERE 制造商全稱:AGERE 功能描述:DSP1629 Digital Signal Processor |
| DSP1629BA10K10IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|BGA|144PIN|PLASTIC |
| DSP1629BA10K12.5IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| DSP1629BA10K16.7IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|BGA|144PIN|PLASTIC |
| DSP1629BA10K19.2IR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。