參數(shù)資料
型號: DSP1628
英文描述: TVS 400W 60V BIDIRECT SMA
中文描述: 澄清,串行I /設(shè)備的DSP1620/27/28/29 O控制注冊說明
文件頁數(shù): 100/114頁
文件大小: 804K
代理商: DSP1628
Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
98
10 Timing Characteristics for 2.7 V Operation
(continued)
Figure 23. PHIF IntelMode Signaling (Pulse Period and Flags) Timing Diagram
* t53 should be referenced to the rising edge of PCSN or PODS, whichever comes first.
t54 should be referenced to the rising edge of
PCSN or PIDS, whichever comes first.
POBE and PIBF may be programmed to be the opposite logic levels shown in the diagram (positive assertion levels shown). t53 and
t54 apply to the inverted levels as well as those shown.
Table 86. Timing Requirements for PHIF IntelMode Signaling
Abbreviated Reference
t55
t56
Parameter
Min
20.5
20.5
Max
Unit
ns
ns
PCSN/PODS/PIDS Pulse Width (high to low)
PCSN/PODS/PIDS Pulse Width (low to high)
Table 87. Timing Characteristics for PHIF IntelMode Signaling
Abbreviated Reference
t53*
Parameter
Min
Max
17
Unit
ns
PCSN/PODS to POBE
(high to high)
PCSN/PIDS to PIBF
(high to high)
t54*
17
ns
PODS
PIDS
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t55
t56
t55
t56
t55
t56
PCSN
t53
t54
16-bit READ
8-bit WRITE
PBSEL
POBE
PIBF
t54
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
t56
t56
t55
t53
8-bit READ
16-bit WRITE
5-4037 (C).a
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