Preliminary Data Sheet
February 1997
DSP1628 Digital Signal Processor
Lucent Technologies Inc.
84
9 Electrical Characteristics and Requirements
(continued)
9.1 Power Dissipation
Power dissipation is highly dependent on DSP program activity and the frequency of operation. The typical power
dissipation listed is for a selected application. The following electrical characteristics are preliminary and are subject
to change.
* T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).
t
L
= PLL lock time (see Table 64).
Table 65. Power Dissipation and Wake-Up Latency
Operating Mode
(Unused inputs at V
DD
or V
SS)
Typical Power Dissipation (mW)
Wake-Up Latency
ECCP Operation
CKI = 40 MHz
V
DD=
3 V
3 V
3 V
3 V
P
ECCP
28.1
—
—
—
I/O Units ON, ECCP OFF
powerc[7:4,0] = 0x01
I/O Units OFF, ECCP OFF
powerc[7:4,0] = 0xF1
(PLL Not Used
During Wake State)
P
DSP
(PLL Used
During Wake State)
Normal Operation ioc = 0x0180
PLL Disabled
CKI & CKO = 40 MHz
CMOS
93.7
96.3
91.2
93.7
—
—
—
—
Small Signal
CKI & CKO = 0 MHz
CMOS
0.17
2.75
0.17
2.75
—
—
—
—
Small Signal
ioc = 0x0180
Normal Operation
PLL Enabled
pllc = 0xFC0E
CKI = 10 MHz CKO = 40 MHz
P
DSP
CMOS
96.7
99.3
94.2
96.7
—
—
—
—
Small Signal
Power Management Modes
CKO = 40 MHz
Standard Sleep, External Interrupt
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
P
SLEEP
CMOS
14.0
16.3
9.3
12.0
3T*
3T*
3T* + t
L
3T* + tL
Small Signal
Standard Sleep, External Interrupt
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS
16.5
18.9
11.2
14.0
—
—
3T*
3T*
Small Signal
Sleep with Slow Internal Clock
Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Disabled During Sleep
CMOS
0.7
3.7
0.5
3.5
5.0
μ
s
5.0
μ
s
5.0
μ
s + t
L
5.0
μ
s + t
L
Small Signal
Sleep with Slow Internal Clock
Small Signal Enabled
powerc[15:14] = 01,
alf[15] = 1, ioc = 0x0180
PLL Enabled During Sleep
CMOS
3.3
6.1
2.9
5.5
—
—
5.0
μ
s
5.0
μ
s
Small Signal