P R E L I M I N A R Y
AMD
1-963
Am79C970
and therefore no transmissions
are attempted. DTX = “0”, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
Read/write accessible only when
STOP bit is set.
Disable Receiver results in
PCnet-PCI controller not access-
ing the Receive Descriptor Ring
and therefore all receive frame
data are ignored. DRX = “0”, will
set RXON bit (CSR0 bit 5) if
STRT (CSR0 bit 1) is asserted.
Read/write accessible only when
STOP bit is set.
0
DRX
CSR16: Initialization Block Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
This register is an alias of CSR1.
15–0IADR[15:0]
CSR17: Initialization Block AddressUpper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
This register is an alias of CSR2.
15–0IADR[31:16]
CSR18: Current Receive Buffer Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current receive buffer address at
which the PCnet-PCI controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0
CRBAL
H_RESET,
CSR19: Current Receive Buffer Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current receive buffer address at
which the PCnet-PCI controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
15–0 CRBAU
unaffected
S_RESET or STOP.
by
H_RESET,
CSR20: Current Transmit Buffer Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current transmit buffer address
from which the PCnet-PCI con-
troller is transmitting.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0
CXBAL
H_RESET,
CSR21: Current Transmit Buffer Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current transmit buffer address
from which the PCnet-PCI con-
troller is transmitting.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 CXBAU
H_RESET,
CSR22: Next Receive Buffer Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next receive buffer address to
which the PCnet-PCI controller
will store incoming frame data.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0
NRBAL
H_RESET,
CSR23: Next Receive Buffer Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next receive buffer address to
which the PCnet-PCI controller
will store incoming frame data.
15–0 NRBAU