參數(shù)資料
型號： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù)： 34/168頁
文件大?。?/td> 943K
代理商： AM79C970
P R E L I M I N A R Y
AMD
1-901
Am79C970
Descriptor DMA Transfers
PCnet-PCI microcode will determine when a descriptor
access is required. A descriptor DMA read will consist of
two DWORD (double-word) transfers. A descriptor
DMA write will consist of one or two DWORD transfers.
(The transfers within a descriptor DMA transfer master-
ship period will always be of the same type (either all
read or all write)).
If buffer chaining is used, writes to the descriptors of all
intermediate buffers consist of only one DWORD to
return OWNership of the buffer to the system. On all sin-
gle buffer transmit or receive descriptors, as well as on
the last buffer in chain, writes to the descriptor consist of
two DWORDs. The first DWORD containing status in-
formation. The second DWORD containing additional
status and the OWNership bit (i.e. MD1[31]).
The transfers will be addressed as specified in tables 1
and 2.
Table 1. Bus Master Reads of Descriptors
Address
Sequence
AD[7:0]*
LANCE/
PCnet-ISA
Item Accessed
Address
Sequence
AD[7:0]*
LANCE/
PCnet-ISA
Item Accessed
PCnet-PCI
Item Accessed
PCnet-PCI
Item Accessed
00
MD1[15:0],
MD0[15:0]
MD1[31:24],
MD0[23:0]
04
MD1[15:8],
MD2[15:0]
MD1[31:0]
04
MD3[15:0],
MD2[15:0]
MD2[15:0],
MD1[15:0]
00
MD1[7:0],
MD0[15:0]
MD0[31:0]
Bus Break
Bus Break
16-Bit Software Mode
32-Bit Software Mode
Table 2. Bus Master Writes to Descriptors
Address
Sequence
AD[7:0]*
LANCE/
PCnet-ISA
Item Accessed
Address
Sequence
AD[7:0]*
LANCE/
PCnet-ISA
Item Accessed
PCnet-PCI
Item Accessed
PCnet-PCI
Item Accessed
04
MD3[15:0],
MD2[15:0]
MD2[15:0],
MD1[15:0]
08
MD3[15:0]
MD2[31:0]
00
MD1[15:0],
MD0[15:0]
MD1[31:24],
MD0[23:0]
04
MD1[15:8],
MD2[15:0]
MD1[31:0]
Bus Break
Bus Break
16-Bit Software Mode
32-Bit Software Mode
* Address values for AD[31:08] are constant throughout any single descriptor DMA transfer. AD[1:0] must be set to ZERO in the
descriptor base address.
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
some of the bytes not be needed, then the PCnet-PCI
controller will internally discard the extraneous informa-
tion that was gathered during such a read. During write
accesses, only the bytes which need to be written are
enabled, by activating the corresponding byte en-
ablepins.
The only significant differences between descriptor
DMA transfers and initialization DMA transfers are that
the addresses of the accesses follow different ordering.
相關(guān)PDF資料
PDF描述
AM79C971VCW PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79C971 PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
AM79C972BKCW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
AM79C972BKIW PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*