參數(shù)資料
型號(hào)： AM79C970
廠(chǎng)商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線(xiàn)
文件頁(yè)數(shù)： 93/168頁(yè)
文件大小： 943K
代理商： AM79C970
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AMD
P R E L I M I N A R Y
1-960
Am79C970
the PCnet-PCI controller initial-
zation routine.
Read accessible only when
STOP bit is set. Write operations
have no effect and should not be
performed. RLEN is only defined
after initialization. These bits are
unaffected by H_RESET, S_RE-
SET or STOP.
Reserved locations. Read as
ZERO. Write operations should
not be performed.
7–0
RES
CSR8: Logical Address Filter, LADRF[15:0]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Logical
Address
LADRF[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 LADRF[15:0]
Filter,
H_RESET,
CSR9: Logical Address Filter LADRF[31:16]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Logical
Address
LADRF[31:16]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct I/O write
has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 LADRF[31:16]
Filter,
H_RESET,
CSR10: Logical Address Filter, LADRF[47:32]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Address
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
15–0 LADRF[47:32] Logical
Filter,
has been set or a direct I/O write
has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
H_RESET,
CSR11: Logical Address Filter, LADRF[63:48]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Logical
Address
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct I/O write
has been performed on this
register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 LADRF[63:48]
Filter,
H_RESET,
CSR12: Physical Address Register, PADR[15:0]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Physical
Address
PADR[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 PADR[15:0]
Register,
H_RESET,
CSR13: Physical Address Register, PADR[31:16]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Physical
Address
PADR[31:16]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct I/O write has been per-
formed on this register.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 PADR[31:16]
Register,
H_RESET,
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970A 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
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