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P R E L I M I N A R Y
AMD
1-883
Am79C970
INTA
Interrupt Request
Input/Output
An asynchronous attention signal which indicates that
one or more of the following status flags is set: BABL,
MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB,
MPCO, or TXSTRT. Each status flag has a mask bit
which allows for suppression of
INTA
assertion. The
flags have the following meaning:
BABL
Babble
RCVCCO
Receive Collision Count Overflow
RPCO
Runt Packet Count Overflow
JAB
Jabber
MISS
Missed Frame
MERR
Memory Error
MPCO
Missed Packet Count Overflow
RINT
Receive Interrupt
IDON
Initialization Done
TXSTRT
Transmit Start
When
RST
is active,
INTA
is an input for NAND tree
testing.
IRDY
Initiator Ready
Input/Output
This signal indicates PCnet-PCI controllers ability, as a
master device, to complete the current data phase of the
transaction.
IRDY
is used in conjunction with the
TRDY
.
A data phase is completed on any clock when both
IRDY
and
TRDY
are asserted. During a write
IRDY
indicates
that valid data is present on AD[31:00]. During a read
IRDY
indicates that data is accepted by the PCnet-PCI
controller as a bus master. Wait states are inserted until
both
IRDY
and
TRDY
are asserted simultaneously.
When
RST
is active,
IRDY
is an input for NAND tree
testing.
LOCK
Lock
Input
LOCK
is used by the current bus master to indicate an
atomic operation that may require multiple transfers.
As a slave device, the PCnet-PCI controller can be
locked by any master device. When another master at-
tempts to access the PCnet-PCI while it is locked, the
PCnet-PCI controller will respond by asserting
DEVSEL
and
STOP
with
TRDY
deasserted (PCI retry).
The PCnet-PCI controller will never assert
LOCK
as a
master.
When
RST
is active,
LOCK
is an input for NAND tree
testing.
PAR
Parity
Input/Output
Parity is even parity across AD[31:00] and
C/
BE
[3:0].When the PCnet-PCI controller is a bus mas-
ter, it generates parity during the address and write data
phases. It checks parity during read data phases. When
the PCnet-PCI controller operates in slave mode and is
the target of the current cycle, it generates parity during
read data phases. It checks parity during address and
write data phases.
When
RST
is active, PAR is an input for NAND tree
testing.
PERR
Parity Error
Input/Output
This signal is asserted by the PCnet-PCI controller
when it checks for parity error during any data phase
when its AD[31:00] lines are inputs. The
PERR
pin is
only active when PERREN (bit 6) in the PCI command
register is set.
The PCnet-PCI controller monitors the
PERR
input dur-
ing a bus master write cycle. It will assert the Data Parity
Reported bit in the Status register of the Configuration
Space when a parity error is reported by the target
device.
When
RST
is active,
PERR
is an input for NAND tree
testing.
REQ
Bus Request
Input/Output
The PCnet-PCI controller asserts
REQ
pin as a signal
that it wishes to become a bus master. Once asserted,
REQ
remains active until
GNT
has become active, inde-
pendent of subsequent assertion of
SLEEP
or setting of
the STOP bit or access to the S_RESET port (off-
set14h).
When
RST
is active,
REQ
is an input for NAND tree
testing.
RST
Reset
Input
When
RST
is asserted low, then the PCnet-PCI control-
ler performs an internal system reset of the type H_RE-
SET (HARDWARE_RESET).
RST
must be held for a
minimum of 30 CLK periods. While in the H_RESET
state, the PCnet-PCI controller will disable or deassert
all outputs.
RST
may be asynchronous to the CLK when
asserted or deasserted. It is recommended that the
deassertion be synchronous to guarantee clean and
bounce free edge.