參數(shù)資料
型號: AM79C970
廠商: Advanced Micro Devices, Inc.
英文描述: PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述: PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù): 130/168頁
文件大?。?/td> 943K
代理商: AM79C970
P R E L I M I N A R Y
AMD
1-997
Am79C970
Register Summary
PCI Configuration Registers
Note: RO = read only, RW = read/write, U = undefined value
Offset
00h
02h
04h
06h
08h
09h
0Ah
0Bh
0Dh
0Eh
10h
3Ch
3Dh
Name
Vendor ID
Device ID
Command
Status
Revision ID
Programming IF
Sub-Class
Base-Class
Latency Timer
Header Type
Base Address
Interrupt Line
Interrupt Pin
Width in Bit
16
16
16
16
8
8
8
8
8
8
32
8
8
Access Mode
RO
RO
RW
RW
RO
RO
RO
RO
RO
RO
RW
RW
RO
Default Value
1022h
2000h
uuuu
uuuu
00h
00h
00h
02h
00h
00h
uuuu uuuu
uu
01h
Control and Status Registers
Note: u = undefined value, R = Running register, S = Setup register, T = Test register
Default Value
After
H_RESET
uuuu 0004
uuuu uuuu
uuuu uuuu
uuuu 0000
uuuu 0115
uuuu 0000
uuuu uuuu
uuuu 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
see reg. desc.
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RAP Addr
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
Symbol
CSR0
CSR1
CSR2
CSR3
CSR4
CSR5
CSR6
CSR7
CSR8
CSR9
CSR10
CSR11
CSR12
CSR13
CSR14
CSR15
CSR16
CSR17
CSR18
CSR22
CSR20
CSR21
Comments
Use
R
S
S
S
R
T
T
T
T
T
T
T
T
T
T
S
T
T
T
T
T
T
PCnet-PCI Status Register
IADR[15:0]: Base Address of INIT Block Lower
IADR[31:16]: Base Address of INIT Block Upper
Interrupt Masks and Deferral Control
Test and Features Control
Reserved
RXTX: RX/TX Descriptor Table Lengths
Reserved
LADR0: Logical Address Filter — LADRF[15:0]
LADR1: Logical Address Filter — LADRF[31:16]
LADR2: Logical Address Filter — LADRF[47:32]
LADR3: Logical Address Filter — LADRF[63:48]
PADR0: Physical Address Register — PADR[15:0]
PADR1: Physical Address Register — PADR[31:16]
PADR2: Physical Address Register — PADR[47:32]
MODE: Mode Register
IADR[15:0]: Alias of CSR1
IADR[31:16]: Alias of CSR2
CRBAL: Current RCV Buffer Address Lower
CRBAU: Current RCV Buffer Address Upper
CXBAL: Current XMT Buffer Address Lower
CXBAU: Current XMT Buffer Address Upper
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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