參數(shù)資料
型號(hào)： AM79C970
廠(chǎng)商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線(xiàn)
文件頁(yè)數(shù)： 15/168頁(yè)
文件大?。?/td> 943K
代理商： AM79C970
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AMD
P R E L I M I N A R Y
1-882
Am79C970
PIN DESCRIPTION
PCI Interface
AD[31:00]
Address and Data Input/Output
These signals are multiplexed on the same PCI pins.
During the first clock of a transaction AD[31:00] contain
the physical byte address (32 bits). During the subse-
quent clocks AD[31:00] contain data. Byte ordering is lit-
tle endian by default. AD[07:00] are defined as least
significant byte and AD[31:24] are defined as the most
significant byte. For FIFO data transfers, the PCnet-PCI
controller can be programmed for big endian byte order-
ing. See CSR3, bit 2 (BSWP) for more details.
During the address phase of the transaction, when the
PCnet-PCI controller is a bus master, AD[31:2] will ad-
dress the active DWORD (double-word). The PCnet-
PCI controller always drives AD[1:0] to ’00’ during the
address phase indicating linear burst order. When the
PCnet-PCI controller is not a bus master, the AD[31:00]
lines are continuously monitored to determine if an ad-
dress match exists for I/O slave transfers.
During the data phase of the transaction, AD[31:00] are
driven by the PCnet-PCI controller when performing bus
master writes and slave read operations. Data on
AD[31:00] is latched by the PCnet-PCI controller when
performing bus master reads and slave write
operations.
When
RST
is active, AD[31:0] are inputs for NAND tree
testing.
C/
BE
[3:0]
Bus Command and Byte Enables
Input/Output
These signals are multiplexed on the same PCI pins.
During the address phase of the transaction, C/
BE
[3:0]
define the bus command. During the data phase
C/
BE
[3:0] are used as Byte Enables. The Byte Enables
define which physical byte lanes carry meaningful data.
C/
BE
0 applies to byte 0 (AD[07:00]) and C/
BE
3 applies
to byte 3 (AD[31:24]). The function of the Byte Enables
is independent of the byte ordering mode (CSR3, bit 2).
When
RST
is active, C/
BE
[3:0] are inputs for NAND tree
testing.
CLK
Clock
Input
This signal provides timing for all the transactions on the
PCI bus and all PCI devices on the bus including the
PCnet-PCI controller. All bus signals are sampled on the
rising edge of CLK and all parameters are defined with
respect to this edge. The PCnet-PCI controller operates
over a range of 0 to 33 MHz.
When
RST
is active, CLK is an input for NAND tree
testing.
DEVSEL
Device Select
Input/Output
This signal when actively driven by the PCnet-PCI con-
troller as a slave device signals to the master device that
the PCnet-PCI controller has decoded its address as the
target of the current access. As an input it indicates
whether any device on the bus has been selected.
When
RST
is active,
DEVSEL
is an input for NAND tree
testing.
FRAME
Cycle Frame
Input/Output
This signal is driven by the PCnet-PCI controller when it
is the bus master to indicate the beginning and duration
of the access.
FRAME
is asserted to indicate a bus
transaction is beginning.
FRAME
is asserted while data
transfers continue.
FRAME
is deasserted when the
transaction is in the final data phase.
When
RST
is active,
FRAME
is an input for NAND tree
testing.
GNT
Bus Grant
Input
This signal indicates that the access to the bus has been
granted to the PCnet-PCI controller.
The PCnet-PCI controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts
GNT
without an active
REQ
from the PCnet-PCI controller,
the PCnet-PCI controller will actively drive the AD, C/
BE
and PAR lines.
When
RST
is active,
GNT
is an input for NAND tree
testing.
IDSEL
Initialization Device Select
Input
This signal is used as a chip select for the PCnet-PCI
controller during configuration read and write
transaction.
When
RST
is active, IDSEL is an input for NAND tree
testing.
相關(guān)PDF資料
PDF描述
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AM79C971 PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970A 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
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