參數(shù)資料
型號: AM79C970
廠商: Advanced Micro Devices, Inc.
英文描述: PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述: PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù): 102/168頁
文件大?。?/td> 943K
代理商: AM79C970
P R E L I M I N A R Y
AMD
1-969
Am79C970
CSR60: Previous Transmit Descriptor
Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
previous TDRE address pointer.
PCnet-PCI controller has the ca-
pability to stack multiple transmit
frames.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0
PXDAL
H_RESET,
CSR61: Previous Transmit Descriptor
Address Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
previous TDRE address pointer.
PCnet-PCI controller has the ca-
pability to stack multiple transmit
frames.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 PXDAU
H_RESET,
CSR62: Previous Transmit Byte Count
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZERO.
Accessible only when STOP bit is
set.
Previous Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the previous
transmit descriptor.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–12
RES
11–0
PXBC
H_RESET,
CSR63: Previous Transmit Status Count
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
15–8
PXST
Previous Transmit Status. This
field is a copy of bits 31–24 of
TMD1 of the previous transmit
descriptor.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
Reserved locations. Read and
written as ZERO.
Accessible only when STOP bit is
set.
H_RESET,
7–0
RES
CSR64: Next Transmit Buffer Address Lower
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next transmit buffer address from
which the PCnet-PCI controller
will transmit an outgoing frame.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0
NXBAL
H_RESET,
CSR65: Next Transmit Buffer Address
Upper
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next transmit buffer address from
which the PCnet-PCI controller
will transmit an outgoing frame.
Read/write accessible only when
STOP bit is set. These bits are
unaffected
by
S_RESET or STOP.
15–0 NXBAU
H_RESET,
CSR66: Next Transmit Byte Count
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Read and
written as ZERO.
Accessible only when STOP bit is
set.
Next Transmit Byte Count. This
field is a copy of the BCNT field of
TMD1 of the next transmit de-
scriptor.
15–12
RES
11–0
NXBC
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