參數(shù)資料
型號(hào)： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù)： 18/168頁
文件大?。?/td> 943K
代理商： AM79C970
P R E L I M I N A R Y
AMD
1-885
Am79C970
configuration registers will be reset by
SLEEP
. All I/O
accesses to the PCnet-PCI controller will result in a PCI
target abort response. The PCnet-PCI controller will not
assert
REQ
while in sleep mode. When
SLEEP
is as-
serted, all non-PCI interface outputs will be placed in
their normal S_RESET condition. All non-PCI interface
inputs will be ignored except for the
SLEEP
pin itself.
De-assertion of
SLEEP
results in wake-up. The system
must refrain from starting the network operations of the
PCnet-PCI device for 0.5 seconds following the
deassertion of the
SLEEP
signal in order to allow inter-
nal analog circuits to stabilize.
Both CLK and XTAL1 inputs must have valid clock sig-
nals present in order for the
SLEEP
command to take
effect. If
SLEEP
is asserted while
REQ
is asserted, then
the PCnet-PCI controller will wait for the assertion of
GNT
. When
GNT
is asserted, the
REQ
signal will be de-
asserted and then the PCnet-PCI controller will proceed
to the power savings mode.
The
SLEEP
pin should not be asserted during power
supply ramp-up. If it is desired that
SLEEP
be asserted
at power up time, then the system must delay the asser-
tion of
SLEEP
until three CLK cycles after the comple-
tion of a valid pin
RST
operation.
XTAL
1 2
Crystal Oscillator Inputs
Input/Output
The crystal frequency determines the network data rate.
The PCnet-PCI controller supports the use of quartz
crystals to generate a 20 MHz frequency compatible
with the ISO 8802-3 (IEEE/ANSI 802.3) network fre-
quency tolerance and jitter specifications. See the sec-
tion External Crystal Characteristics (in section
Manchester Encoder/Decoder) for more detail.
The network data rate is one-half of the crystal fre-
quency. XTAL1 may alternatively be driven using an ex-
ternal CMOS level source, in which case XTAL2 must
be left unconnected. Note that when the PCnet-PCI con-
troller is in comma mode, there is an internal 22 K
re-
sistor from XTAL1 to ground. If an external source drives
XTAL1, some power will be consumed driving this resis-
tor. If XTAL1 is driven LOW at this time power consump-
tion will be minimized. In this case, XTAL1 must remain
active for at least 30 cycles after the assertion of
SLEEP
and deassertion of
REQ
.
Microwire EEPROM Interface
EESK
EEPROM Serial clock
Input/Output
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EESK is
connected to the Microwire EEPROMs Clock pin. It is
controlled by either the PCnet-PCI controller directly
during a read of the entire EEPROM, or indirectly by the
host system by writing to BCR19, bit 1.
The EESK pin is also used during EEPROM Auto-detec-
tion to determine whether or not an EEPROM is present
at the PCnet-PCI controller Microwire interface. At the
trailing edge of the
RST
signal,
LED1
is sampled to de-
termine the value of the EEDET bit in BCR19. A sam-
pled HIGH value means that an EEPROM is present,
and EEDET will be set to ONE. A sampled LOW value
means that an EEPROM is not present, and EEDET will
be set to ZERO. See the EEPROM Auto-detection sec-
tion for more details.
EESK is shared with the LED1 function. If no LED circuit
is to be attached to this pin, then a pull up or pull down
resistor must be attached instead, in order to resolve the
EEDET setting.
EEDO
EEPROM Data Out
Input
The EEDO signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the Microwire interface protocol. EEDO is con-
nected to the Microwire EEPROMs Data Output pin. It is
controlled by the EEPROM during reads. It may be read
by the host system by reading BCR19 bit 0.
EEDO is shared with the LED3 function.
EECS
EEPROM Chip Select
Output
The function of the EECS signal is to indicate to the
Microwire EEPROM device that it is being accessed.
The EECS signal is active high. It is controlled by either
the PCnet-PCI controller during command portions of a
read of the entire EEPROM, or indirectly by the host sys-
tem by writing to BCR19 bit 2.
EEDI
EEPROM Data In
Output
The EEDI signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. EEDI func-
tions as an output. This pin is designed to directly inter-
face to a serial EEPROM that uses the Microwire
interface protocol. EEDI is connected to the Microwire
EEPROMs Data Input pin. It is controlled by either the
PCnet-PCI controller during command portions of a
read of the entire EEPROM, or indirectly by the host sys-
tem by writing to BCR19 bit 0.
EEDI is shared with the LNKST function.
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